component
XT2052Y2ASR-G
Public Made by Adomby adom
NATLINEAR Battery Management, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no net (vendor string 'SOP-8-EP' denotes an exposed pad)
4 files changed
+16−22
pads.json+7−20@@ -26,24 +26,11 @@ "5", "6", "7",- "8"+ "8",+ "9" ], "paste_apertures": 4,- "issues": [- {- "kind": "pin-not-in-symbol",- "pin": "EP",- "name": "EPAD",- "detail": "page.json describes pin \"EP\" (EPAD) from the datasheet, but the symbol has no such pin, so nothing can connect to it"- },- {- "kind": "pad-has-no-pin",- "pad": "9",- "thermal": true,- "described_in_page": false,- "detail": "footprint pad \"9\" is in copper but the SYMBOL has no pin for it - a thermal pad with no net will float"- }- ],+ "issues": [], "pads": [ { "pad": "1",@@ -301,13 +288,13 @@ "layers": [], "thermal": true, "pin": "9",- "name": null,- "type": null,- "description": null,+ "name": "EPAD",+ "type": "power_in",+ "description": "Exposed thermal pad on the underside of the package. Must be soldered to the GND copper plane and tied to pin 3 for proper thermal performance, especially in high-current (up to 1.0A / 1.2A) applications.", "is_pin1": false, "source": { "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",- "meaning": null,+ "meaning": "page.json:component.pins", "correspondence": "kicad: symbol pin number == pad name" } }
page.json+3−2@@ -77,10 +77,11 @@ "description": "No internal connection. Leave floating or tie to GND for improved layout." }, {- "number": "EP",+ "number": "9", "name": "EPAD", "type": "power_in",- "description": "Exposed thermal pad on the underside of the package. Must be soldered to the GND copper plane and tied to pin 3 for proper thermal performance, especially in high-current (up to 1.0A / 1.2A) applications."+ "description": "Exposed thermal pad on the underside of the package. Must be soldered to the GND copper plane and tied to pin 3 for proper thermal performance, especially in high-current (up to 1.0A / 1.2A) applications.",+ "source": "renumbered-to-footprint-pad" } ], "provenance": {
xt2052y2asr-g.kicad_sym+4@@ -40,6 +40,10 @@ (name "VBAT" (effects (font (size 1.27 1.27)))) (number "5" (effects (font (size 1.27 1.27)))) )+ (pin power_in line (at -17.78 -7.62 0) (length 5.08)+ (name "EPAD" (effects (font (size 1.27 1.27))))+ (number "9" (effects (font (size 1.27 1.27))))+ ) ) ) )
xt2052y2asr-g.lbr+2@@ -89,6 +89,7 @@ <pin name="CHRG" x="17.78" y="0" length="middle" direction="out" rot="R180"/> <pin name="DONE" x="17.78" y="-2.54" length="middle" direction="out" rot="R180"/> <pin name="VBAT" x="17.78" y="-5.08" length="middle" direction="out" rot="R180"/>+ <pin name="EPAD" x="-17.78" y="-7.62" length="middle" direction="pwr"/> </symbol> </symbols> <devicesets>@@ -108,6 +109,7 @@ <connect gate="G$1" pin="CHRG" pad="7"/> <connect gate="G$1" pin="DONE" pad="6"/> <connect gate="G$1" pin="VBAT" pad="5"/>+ <connect gate="G$1" pin="EPAD" pad="9"/> </connects> <technologies><technology name=""/></technologies> </device>