XPD977D30A

@@ -0,0 +1,73 @@+# XPD977D30A++**Shenzhen Fuman** · USB Converters · QFN-32-EP(5x5)++XPD977D30A from Shenzhen Fuman, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VFB | input | System voltage feedback pin - connects to the AC-DC / DC-DC power stage feedback node so XPD977 can dynamically adjust output voltage. |+| 2 | IREF | passive | CC loop compensation pin. Recommended RC network R=10 kΩ, C=10 nF to GND. Leave floating if the CC function is not used. |+| 3 | CSN | input | Main current-sense negative input. Tie to GND if unused; must not be left floating. |+| 4 | CSP | input | Main current-sense positive input, across the 10 mΩ constant-current sense resistor R_S1. Tie to GND if unused; must not be left floating. |+| 5 | ISP2 | input | Type-A2 port current-sense positive input, across the 5 mΩ R_S2 sense resistor. |+| 6 | ISP3 | input | Type-A3 port current-sense positive input, across the 5 mΩ R_S3 sense resistor. |+| 7 | DP3 | bidirectional | Type-A3 port USB D+ data line (BC1.2 / QC / FCP / AFC / Apple 2.4A handshaking). |+| 8 | LINK | bidirectional | XPD-LINK inter-chip communication bus. Pull to GND through R_LINK = 10 kΩ. Used to coordinate multi-chip charger designs. |+| 9 | DM3 | bidirectional | Type-A3 port USB D- data line. |+| 10 | DIS | output | Gate control for external discharge NMOS transistor used to bleed VBUS down between transitions. |+| 11 | AISN | input | Interconnect current-sense negative input, used when linking to a non-XPD-series companion chip. Tie to GND if unused. |+| 12 | AISP | input | Interconnect current-sense positive input, used when linking to a non-XPD-series companion chip. Tie to GND if unused. |+| 13 | USBA3 | power_out | Type-A3 port VBUS output rail (routes through external Type-A3 PMOS switch driven by GD3). |+| 14 | GD3 | output | Gate-drive output for the external Type-A3 port PMOS pass switch. Requires a 47 nF C_GATE2 hold capacitor per spec table. |+| 15 | DP2 | bidirectional | Type-A2 port USB D+ data line. |+| 16 | DM2 | bidirectional | Type-A2 port USB D- data line. |+| 17 | USBA2 | power_out | Type-A2 port VBUS output rail (routes through external Type-A2 PMOS switch driven by GD2). |+| 18 | GD2 | output | Gate-drive output for the external Type-A2 port PMOS pass switch. Requires a 47 nF C_GATE1 hold capacitor per spec table. |+| 19 | CC1 | bidirectional | USB Type-C CC1 configuration channel - orientation detect and PD BMC signalling. Rated to 26 V with internal OVP. |+| 20 | DP1 | bidirectional | USB Type-C port data line (labelled DP1 on package; datasheet description reads 'Type-C 口数据端口 DM'). |+| 21 | DM1 | bidirectional | USB Type-C port data line (labelled DM1 on package; datasheet description reads 'Type-A 口数据端口 DP'). |+| 22 | CC2 | bidirectional | USB Type-C CC2 configuration channel - orientation detect and PD BMC signalling. Rated to 26 V with internal OVP. |+| 23 | VBUS | power_out | USB Type-C VBUS output rail. Pins 23/24/25 are internally tied - bulk decoupling C_VBUS 1-10 µF required. Rating: -0.3 to 26 V. |+| 24 | VBUS | power_out | USB Type-C VBUS output rail (tied to pins 23 and 25). |+| 25 | VBUS | power_out | USB Type-C VBUS output rail (tied to pins 23 and 24). Internal 10 mΩ VBUS switch and discharge path terminate here. |+| 26 | NC | unconnected | No connect - leave floating. |+| 27 | NC | unconnected | No connect - leave floating. |+| 28 | VPWR | power_in | Chip supply input. Operating range 3.3-21 V (abs max 26 V). Requires C_VPWR bulk cap 1-10 µF. Pins 28/29/30 are internally tied. |+| 29 | VPWR | power_in | Chip supply input (tied to pins 28 and 30). UVLO rising 3.3 V / falling 2.9 V. |+| 30 | VPWR | power_in | Chip supply input (tied to pins 28 and 29). |+| 31 | NC | unconnected | No connect - leave floating. |+| 32 | OPTO | output | Optocoupler driver output used to feed back the primary-side controller through R_FB1 in AC-DC applications. |+| 33 | EPAD | power_in | Exposed thermal pad on the QFN underside - die ground. Must be soldered to the PCB GND plane for both electrical return and thermal dissipation (θJA = 34 °C/W). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Shenzhen Fuman |+| Package | QFN-32-EP(5x5) |+| Category | Interface |+| Pins | 33 |++## Ordering variants++- `XPD977D30AD30A`++## CAD (KiCad official)++- Symbol: `XPD977D30A`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Shenzhen Fuman datasheet](docs/xpd977d30a-datasheet.pdf) (19 pp, sha256 `d7f28524b33b1f03`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/xpd977d30a-datasheet.pdf)

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