component
XL74HC597
Public Made by Adomby adom
XINLUDA Shifting Register, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+164−8@@ -1,13 +1,174 @@ {+ "schema_version": 1,+ "type": "component", "slug": "xl74hc597",+ "title": "XL74HC597",+ "brief": "XINLUDA Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "XINLUDA Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "xl74hc597" ],+ "component": {+ "mpn": "XL74HC597",+ "manufacturer": "XINLUDA",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shifting Register",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/16e077a3040c7bbc7e84ccc252f1352d.pdf",+ "parts": {+ "symbol": "xl74hc597.kicad_sym",+ "footprint": "xl74hc597.kicad_mod",+ "model_3d": "xl74hc597.glb",+ "model_3d_step": "xl74hc597.step",+ "lbr": "xl74hc597.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "D1",+ "type": "input",+ "description": "Parallel data input bit 1 to the 8-bit input storage (flip-flop) register. CMOS-level input; latched to the storage register on the rising edge of STCP."+ },+ {+ "number": "2",+ "name": "D2",+ "type": "input",+ "description": "Parallel data input bit 2 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP."+ },+ {+ "number": "3",+ "name": "D3",+ "type": "input",+ "description": "Parallel data input bit 3 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP."+ },+ {+ "number": "4",+ "name": "D4",+ "type": "input",+ "description": "Parallel data input bit 4 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP."+ },+ {+ "number": "5",+ "name": "D5",+ "type": "input",+ "description": "Parallel data input bit 5 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP."+ },+ {+ "number": "6",+ "name": "D6",+ "type": "input",+ "description": "Parallel data input bit 6 to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP."+ },+ {+ "number": "7",+ "name": "D7",+ "type": "input",+ "description": "Parallel data input bit 7 (MSB) to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). All voltages are referenced to this pin."+ },+ {+ "number": "9",+ "name": "Q",+ "type": "output",+ "description": "Serial data output - tap from the last stage of the 8-bit shift register. Push-pull CMOS output rated for IO up to \u00b125 mA (absolute max); VOH \u2265 VCC-0.1 V at IO = -20 \u00b5A."+ },+ {+ "number": "10",+ "name": "MR",+ "type": "input",+ "description": "Asynchronous master reset input, active LOW. Driving MR LOW while PL is HIGH clears the 8-bit shift register regardless of the clocks."+ },+ {+ "number": "11",+ "name": "SHCP",+ "type": "input",+ "description": "Shift-register clock input. Positive edge-triggered (LOW-to-HIGH): each rising edge shifts DS into Q0 and propagates all bits toward Q. Max frequency 30 MHz min at VCC = 4.5 V (typ 87 MHz)."+ },+ {+ "number": "12",+ "name": "STCP",+ "type": "input",+ "description": "Storage-register clock input. Positive edge-triggered (LOW-to-HIGH): each rising edge loads the D0-D7 parallel inputs into the 8-bit input storage (flip-flop) register."+ },+ {+ "number": "13",+ "name": "PL",+ "type": "input",+ "description": "Parallel-load input, active LOW. Asserting PL LOW (with MR HIGH) transfers the contents of the input storage register in parallel into the 8-bit shift register."+ },+ {+ "number": "14",+ "name": "DS",+ "type": "input",+ "description": "Serial data input to the shift register. Sampled on the rising edge of SHCP and loaded into Q0 during serial-shift operation."+ },+ {+ "number": "15",+ "name": "D0",+ "type": "input",+ "description": "Parallel data input bit 0 (LSB) to the 8-bit input storage register. CMOS-level input; latched on the rising edge of STCP."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage. Recommended operating range 2.0 V to 6.0 V (typ 5.0 V); absolute maximum -0.5 V to +7 V."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/16e077a3040c7bbc7e84ccc252f1352d.pdf",+ "pages": 16,+ "sha256": "8e0ebbf85b427db7",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "XINLUDA",+ "Package": "SOP-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "xl74hc597"+ ],+ "discovery_pitch": "XL74HC597 (XINLUDA) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +186,5 @@ "docs/xl74hc597-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }