XL7046E1

@@ -0,0 +1,48 @@+# XL7046E1++**XLSEMI** · DC-DC Converters · ESOP-8++XL7046E1 from XLSEMI, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CSN | input | Current Sense Negative terminal. Connects to the low side of the external current-sense resistor R3 (typ. 0.075 Ω for VOUT ≤ 5V, 0.082 Ω for VOUT > 5V) used to program the switch current limit (typ. 1.1 A). |+| 2 | CSP | input | Current Sense Positive terminal. Connects to the high side of the external current-sense resistor for the internal over-current-sense (OCS) comparator that enforces the switch current limit. |+| 3 | VC | passive | Internal voltage regulator bypass capacitor pin. In a typical application, connect a 1 µF capacitor from VC to VIN to decouple the internal bias regulator. |+| 4 | VIN | power_in | Supply voltage input pin. The XL7046 operates from 8V to 80V DC (absolute max 90V). Bypass VIN to GND with a suitably large capacitor (e.g. 47 µF/100V) to eliminate input noise. |+| 5 | SW | output | Power switch output pin. This is the switch node that supplies power to the output through the external inductor and freewheeling Schottky diode. The exposed pad is electrically SW. Absolute rating -0.3V to VIN. |+| 6 | EN | input | Enable pin (TTL shutdown). Drive EN high (≥2V) to turn the device OFF; drive low (≤1V) or connect to GND to enable the regulator. Floating defaults low (enabled). Absolute rating -0.3V to 20V. |+| 7 | GND | power_in | Ground pin. Care must be taken in layout: this pin should be placed outside of the Schottky diode to output-capacitor ground path to prevent switching current spikes from inducing voltage noise into the XL7046. |+| 8 | FB | input | Feedback pin. Through an external resistor divider, FB senses the output voltage and regulates it to the 1.25V feedback threshold. VOUT = 1.25 × (1 + R2/R1). Absolute rating -0.3V to 5V. |+| 9 | EP | output | Exposed thermal pad on the underside of the SOP8-EP package. Electrically connected to the SW node (per Figure 2 note 'The Exposed PAD is SW'). Must be tied to the SW copper island on the PCB for heat dissipation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | XLSEMI |+| Package | ESOP-8 |+| Category | PMIC |+| Pins | 9 |++## Ordering variants++- `XL7046E1E1`++## CAD (KiCad official)++- Symbol: `XL7046E1`+- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`+- 3D model: ESOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [XLSEMI datasheet](docs/xl7046e1-datasheet.pdf) (12 pp, sha256 `bfa135c6ec9c4c7a`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/xl7046e1-datasheet.pdf)

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