component
XL555
Public Made by Adomby adom
XINLUDA Timers / Clock Oscillators, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+10−7@@ -38,19 +38,19 @@ "number": "2", "name": "TRIG", "type": "input",- "description": "Trigger input. Start of timing input; when TRIG falls below 1/2 CONT (\u22481/3 VDD) the internal flip-flop is set, driving OUT high and opening the DISCH transistor. Input current \u224810 pA typical."+ "description": "Trigger input. Start of timing input; when TRIG falls below 1/2 CONT (≈1/3 VDD) the internal flip-flop is set, driving OUT high and opening the DISCH transistor. Input current ≈10 pA typical." }, { "number": "3", "name": "OUT", "type": "output",- "description": "High-current timer output signal (rail-to-rail CMOS). Sink capability 100 mA (max), source \u224810 mA typical."+ "description": "High-current timer output signal (rail-to-rail CMOS). Sink capability 100 mA (max), source ≈10 mA typical." }, { "number": "4", "name": "RESET", "type": "input",- "description": "Active-low reset input. Overrides all other inputs: when driven low the flip-flop is reset, OUT goes low and DISCH is pulled low. Typical VRESET \u22481.1 V; tie to VDD if unused."+ "description": "Active-low reset input. Overrides all other inputs: when driven low the flip-flop is reset, OUT goes low and DISCH is pulled low. Typical VRESET ≈1.1 V; tie to VDD if unused." }, { "number": "5",@@ -62,19 +62,19 @@ "number": "6", "name": "THRES", "type": "input",- "description": "Threshold (end-of-timing) input. When THRES rises above CONT (\u22482/3 VDD) the flip-flop is reset, OUT goes low and DISCH is pulled low. Input current \u224810 pA typical."+ "description": "Threshold (end-of-timing) input. When THRES rises above CONT (≈2/3 VDD) the flip-flop is reset, OUT goes low and DISCH is pulled low. Input current ≈10 pA typical." }, { "number": "7", "name": "DISCH", "type": "output",- "description": "Discharge. Open-collector/open-drain output used to discharge the external timing capacitor. Saturation voltage \u224850 mV at 1 mA; leakage \u22481 nA typical."+ "description": "Discharge. Open-collector/open-drain output used to discharge the external timing capacitor. Saturation voltage ≈50 mV at 1 mA; leakage ≈1 nA typical." }, { "number": "8", "name": "VDD", "type": "power_in",- "description": "Positive supply, 2 V to 16 V (absolute max 18 V). Typical supply current 120 \u00b5A at VDD = 5 V."+ "description": "Positive supply, 2 V to 16 V (absolute max 18 V). Typical supply current 120 µA at VDD = 5 V." } ], "provenance": {@@ -138,5 +138,8 @@ "docs/xl555-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }