component
XC6220B331MR-G
Public Made by Adomby adom
Torex Semicon Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-25. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C86534). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+26−6
page.json+6−4@@ -26,13 +26,15 @@ "model_3d_step": "xc6220b331mr-g.step", "lbr": "xc6220b331mr-g.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C86534"+ }, "pins": [ { "number": "1", "name": "VIN", "type": "power_in",- "description": "Power input. Operating range 1.6V-6.0V (absolute max VSS-0.3 to +6.5V). Bypass with a ceramic capacitor (typ. 1 µF) close to the pin."+ "description": "Power input. Operating range 1.6V-6.0V (absolute max VSS-0.3 to +6.5V). Bypass with a ceramic capacitor (typ. 1 \u00b5F) close to the pin." }, { "number": "2",@@ -44,7 +46,7 @@ "number": "3", "name": "CE", "type": "input",- "description": "Chip Enable (ON/OFF control). VCE ≤ 0.4V = OFF (stand-by), 1.2V ≤ VCE ≤ 6.0V = ON. Absolute max VSS-0.3 to +6.5V. Do not leave open on A/B series (undefined); C/D series has internal pull-down."+ "description": "Chip Enable (ON/OFF control). VCE \u2264 0.4V = OFF (stand-by), 1.2V \u2264 VCE \u2264 6.0V = ON. Absolute max VSS-0.3 to +6.5V. Do not leave open on A/B series (undefined); C/D series has internal pull-down." }, { "number": "4",@@ -56,7 +58,7 @@ "number": "5", "name": "VOUT", "type": "power_out",- "description": "Regulated output, factory-trimmed to 3.3V (0.8V-5.0V range in family). Output current up to 1000mA (limit ~1200mA typ). Requires a low-ESR ceramic output capacitor CL (typ. 1 µF; 22 µF for inrush spec)."+ "description": "Regulated output, factory-trimmed to 3.3V (0.8V-5.0V range in family). Output current up to 1000mA (limit ~1200mA typ). Requires a low-ESR ceramic output capacitor CL (typ. 1 \u00b5F; 22 \u00b5F for inrush spec)." } ], "provenance": {
xc6220b331mr-g.lbr+20−2@@ -59,6 +59,18 @@ <smd name="3" x="-1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/> <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/> <smd name="5" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-1.4500" y="1.5100"/>+ <vertex x="-1.6900" y="1.8400"/>+ <vertex x="-1.2100" y="1.8400"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.4000" y="1.4500"/>+ <vertex x="0.8000" y="1.4500"/>+ <vertex x="0.8000" y="-1.4500"/>+ <vertex x="-0.8000" y="-1.4500"/>+ <vertex x="-0.8000" y="1.0500"/>+ </polygon> <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@ <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/> <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="XC6220B331MR-G">@@ -100,7 +112,13 @@ <connect gate="G$1" pin="VOUT" pad="5"/> <connect gate="G$1" pin="NC" pad="4"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="XC6220B331MR-G" constant="no"/>+ <attribute name="MANUFACTURER" value="Torex Semicon" constant="no"/>+ <attribute name="LCSC_PN" value="C86534" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>