VIPER12ASTR-E

@@ -0,0 +1,49 @@+# VIPER12ASTR-E++**STMicroelectronics** · AC-DC Controllers and Regulators · SO-8++VIPER12ASTR-E from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SOURCE | power_in | Power MOSFET source and circuit ground reference. Tied together with pin 2 (both SOURCE pins are the internal MOSFET source and the IC ground reference). |+| 2 | SOURCE | power_in | Power MOSFET source and circuit ground reference. Second SOURCE pin, internally connected to pin 1. |+| 3 | FB | input | Feedback input. Useful voltage range extends from 0 V to 1 V and defines the peak drain MOSFET current. Current limitation (maximum drain current) is obtained by shorting FB to SOURCE. Input impedance R_FB ~ 1.2 kΩ; I_FB shutdown current ~ 0.9 mA. |+| 4 | VDD | power_in | Power supply of the control circuits (9 V to 38 V operating range). Also provides charging current during start-up via the high-voltage current source connected to DRAIN. Hysteresis comparator monitors VDD with V_DDon ≈ 14.5 V (starts switching, turns off start-up current source) and V_DDoff ≈ 8 V (stops switching, turns on start-up current source). V_DDovp ≈ 42 V overvoltage threshold. |+| 5 | DRAIN | power_out | Power MOSFET drain. Also used by the internal high-voltage current source during start-up phase to charge the external VDD capacitor. BV_DSS = 730 V. Pins 5, 6, 7, 8 are internally connected together (multiple DRAIN pins improve thermal dissipation - connect all to the drain node and copper pour, at least 200 mm² of 35 µm Cu). |+| 6 | DRAIN | power_out | Power MOSFET drain. Internally connected to pins 5, 7 and 8. Tie to the drain net for thermal spreading. |+| 7 | DRAIN | power_out | Power MOSFET drain. Internally connected to pins 5, 6 and 8. Tie to the drain net for thermal spreading. |+| 8 | DRAIN | power_out | Power MOSFET drain. Internally connected to pins 5, 6 and 7. Tie to the drain net for thermal spreading. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | SO-8 |+| Category | PMIC |+| Pins | 8 |++## Ordering variants++- `VIPER12ASTR-E`+- `VIPER12ASTR-EVIPER12AS-E`+- `VIPER12ASTR-EVIPER12ADIP-E`++## CAD (KiCad official)++- Symbol: `VIPER12ASTR-E`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SO-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/viper12astr-e.pdf) (21 pp, sha256 `7311adf78816dd66`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/viper12astr-e-datasheet.pdf)

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