USB2514BI-AEZG-TR

@@ -0,0 +1,76 @@+# USB2514BI-AEZG-TR++**Microchip** · USB Converters · TQFN-36-EP(6x6)++USB2514BI-AEZG-TR from Microchip, in a TQFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | USBDM_DN1/PRT_DIS_M1 | bidirectional | Downstream USB 2.0 port 1 D- data line (analog IO-U). At RESET_N negation, doubles as PRT_DIS_M1 strap: pull both PRT_DIS_M1 and PRT_DIS_P1 high (47-100 k) to disable port 1. |+| 2 | USBDP_DN1/PRT_DIS_P1 | bidirectional | Downstream USB 2.0 port 1 D+ data line (analog IO-U). Also serves as PRT_DIS_P1 disable strap (with PRT_DIS_M1) sampled at RESET_N negation. |+| 3 | USBDM_DN2/PRT_DIS_M2 | bidirectional | Downstream USB 2.0 port 2 D- data line. Doubles as PRT_DIS_M2 disable strap sampled at RESET_N negation. |+| 4 | USBDP_DN2/PRT_DIS_P2 | bidirectional | Downstream USB 2.0 port 2 D+ data line. Doubles as PRT_DIS_P2 disable strap. |+| 5 | VDDA33 | power_in | 3.3 V analog supply pin. Bypass locally to VSS. |+| 6 | USBDM_DN3/PRT_DIS_M3 | bidirectional | Downstream USB 2.0 port 3 D- data line. Doubles as PRT_DIS_M3 disable strap sampled at RESET_N negation. |+| 7 | USBDP_DN3/PRT_DIS_P3 | bidirectional | Downstream USB 2.0 port 3 D+ data line. Doubles as PRT_DIS_P3 disable strap. |+| 8 | USBDM_DN4/PRT_DIS_M4 | bidirectional | Downstream USB 2.0 port 4 D- data line. Doubles as PRT_DIS_M4 disable strap sampled at RESET_N negation. |+| 9 | USBDP_DN4/PRT_DIS_P4 | bidirectional | Downstream USB 2.0 port 4 D+ data line. Doubles as PRT_DIS_P4 disable strap. |+| 10 | VDDA33 | power_in | 3.3 V analog supply pin. Bypass locally to VSS. |+| 11 | TEST | input | Factory test pin with internal pull-down (IPD). Treat as no-connect or tie to ground; no trace or signal should be routed to this pin. |+| 12 | PRTPWR1/BC_EN1 | output | Port 1 USB power enable output (O12, 12 mA) to the external port-power switch. At RESET_N negation the pin is sampled as BC_EN1 (IPD) strap: 1 = enable Battery Charging on port 1, 0 = disable. |+| 13 | OCS_N1 | input | Over-current sense input for port 1 from an external current monitor. Active low; internal pull-up (IPU). |+| 14 | CRFILT | passive | VDD core regulator filter capacitor pin. Can have up to 0.1 uF low-ESR capacitor to VSS, or be left unconnected. |+| 15 | VDD33 | power_in | 3.3 V digital power supply. Bypass locally to VSS. |+| 16 | PRTPWR2/BC_EN2 | output | Port 2 USB power enable output (O12, 12 mA). At RESET_N negation the pin is sampled as BC_EN2 strap to enable/disable Battery Charging on port 2. |+| 17 | OCS_N2 | input | Over-current sense input for port 2 from an external current monitor. Active low; internal pull-up. |+| 18 | PRTPWR3/BC_EN3 | output | Port 3 USB power enable output (O12, 12 mA). At RESET_N negation the pin is sampled as BC_EN3 strap to enable/disable Battery Charging on port 3. |+| 19 | OCS_N3 | input | Over-current sense input for port 3 from an external current monitor. Active low; internal pull-up. |+| 20 | PRTPWR4/BC_EN4 | output | Port 4 USB power enable output (O12, 12 mA). At RESET_N negation the pin is sampled as BC_EN4 strap to enable/disable Battery Charging on port 4. |+| 21 | OCS_N4 | input | Over-current sense input for port 4 from an external current monitor. Active low; internal pull-up. |+| 22 | SDA/SMBDATA/NON_REM1 | bidirectional | Serial data: I2C EEPROM data line or SMBus slave data (I/OSD12, open-drain, 12 mA sink). At RESET_N negation, also sampled as NON_REM1 strap (with NON_REM0) to mark ports as non-removable/compound-device. |+| 23 | VDD33 | power_in | 3.3 V digital power supply. Bypass locally to VSS. |+| 24 | SCL/SMBCLK/CFG_SEL0 | bidirectional | Serial clock: I2C EEPROM clock or SMBus slave clock (I/OSD12, open-drain, 12 mA sink). Also latched on RESET_N rising edge as CFG_SEL0 to select configuration source per Table 5.1. |+| 25 | HS_IND/CFG_SEL1 | bidirectional | Hi-Speed upstream port indicator (I/O12): asserted when hub connected at HS, negated at FS; can drive an LED. Also latched on RESET_N rising edge as CFG_SEL1 for configuration-source selection. |+| 26 | RESET_N | input | Active-low system reset input with Schmitt trigger (IS). Minimum active-low pulse width 1 us; strap pins are latched on rising edge (negation). |+| 27 | VBUS_DET | input | Upstream VBUS power detect input. Determines when the internal upstream D+ pull-up is asserted (connect event). For detachable hubs, connect to upstream VBUS via a 2:1 divider (two 100 k resistors); for self-powered fixed-host designs, tie to host control or the 3.3 V rail powering the host. |+| 28 | SUSP_IND/LOCAL_PWR/NON_REM0 | bidirectional | Multi-function pin. As SUSP_IND: I/O status output indicating hub configured and active (asserted) vs unconfigured/suspend. As LOCAL_PWR: input indicating availability of local self-power (high = self-power available). Also sampled at RESET_N negation as NON_REM0 strap (with NON_REM1) to mark non-removable ports; can drive an LED. |+| 29 | VDDA33 | power_in | 3.3 V analog supply pin. Bypass locally to VSS. |+| 30 | USBDM_UP | bidirectional | Upstream USB 2.0 D- data line (analog IO-U). Connects to the host/upstream hub D-. |+| 31 | USBDP_UP | bidirectional | Upstream USB 2.0 D+ data line (analog IO-U). Connects to the host/upstream hub D+. |+| 32 | XTALOUT | output | 24 MHz crystal driver output (OCLKx), 1.2 V p-p, weak (<1 mA) drive strength. Leave unconnected when driving XTALIN/CLKIN from an external oscillator. |+| 33 | XTALIN/CLKIN | input | 24 MHz crystal input (ICLKx) or external 24 MHz clock input. Connect one crystal terminal here, or drive with an external 24 MHz single-ended clock. |+| 34 | PLLFILT | passive | PLL regulator filter capacitor pin. Can have up to 0.1 uF low-ESR capacitor to VSS, or be left unconnected. |+| 35 | RBIAS | passive | USB transceiver bias. Connect a 12.0 kOhm (+/-1%) resistor from this pin to ground to set the transceiver's internal bias. |+| 36 | VDDA33 | power_in | 3.3 V analog supply pin. Bypass locally to VSS. |+| 37 | VSS | power_in | Exposed ground pad (ePad). This is the ONLY VSS connection for the device and must be tied to ground with multiple vias for both electrical and thermal performance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Microchip |+| Package | TQFN-36-EP(6x6) |+| Category | Interface |+| Pins | 37 |++## Ordering variants++- `USB2514BI-AEZG-TR`++## CAD (KiCad official)++- Symbol: `USB2514BI-AEZG-TR`+- Footprint: `Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm`+- 3D model: TQFN-36-EP(6x6) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Microchip datasheet](docs/usb2514bi-aezg-tr-datasheet.pdf) (62 pp, sha256 `23a2bdee11ebed45`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/usb2514bi-aezg-tr-datasheet.pdf)

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