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Initial commit: component/uln2003cdrg

Ray ·08d3ce5b5e ·6d ago
2 files changed +241
README.mdadded+53
@@ -0,0 +1,53 @@+# ULN2003CDRG++**HANSCHIP semiconductor** · Darlington Transistor Arrays · SOP-16++ULN2003CDRG from HANSCHIP semiconductor, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN1 | input | Channel 1 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V. |+| 2 | IN2 | input | Channel 2 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V. |+| 3 | IN3 | input | Channel 3 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V. |+| 4 | IN4 | input | Channel 4 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V. |+| 5 | IN5 | input | Channel 5 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V. |+| 6 | IN6 | input | Channel 6 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V. |+| 7 | IN7 | input | Channel 7 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V. |+| 8 | GND | power_in | Common emitter return; all seven NPN Darlington pair emitters tied to this pin; connect to ground. |+| 9 | COM | power_in | Common cathode of internal flyback suppression diodes; connect to inductive-load supply rail; withstands up to 50 V off-state. |+| 10 | OUT7 | output | Channel 7 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V. |+| 11 | OUT6 | output | Channel 6 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V. |+| 12 | OUT5 | output | Channel 5 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V. |+| 13 | OUT4 | output | Channel 4 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V. |+| 14 | OUT3 | output | Channel 3 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V. |+| 15 | OUT2 | output | Channel 2 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V. |+| 16 | OUT1 | output | Channel 1 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | HANSCHIP semiconductor |+| Package | SOP-16 |+| Category | Transistors/Thyristors |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `ULN2003CDRG`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)+- 3D model files: `uln2003cdrg-etched.step` / `uln2003cdrg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uln2003cdrg.step` / `uln2003cdrg.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [HANSCHIP semiconductor datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590456765947928576) (8 pp, sha256 `97f33aca6df18240`, retrieved 2026-09-29, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/uln2003cdrg-datasheet.pdf)
page.jsonadded+188
@@ -0,0 +1,188 @@+{+  "slug": "uln2003cdrg",+  "version": "0.1.0",+  "type": "component",+  "description": "HANSCHIP semiconductor Darlington Transistor Arrays, SOP-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "transistors-thyristors",+    "uln2003cdrg",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "uln2003cdrg.kicad_sym",+    "uln2003cdrg.kicad_mod",+    "uln2003cdrg.glb",+    "uln2003cdrg.step",+    "uln2003cdrg.lbr",+    "docs/hero.png",+    "docs/uln2003cdrg-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "ULN2003CDRG",+    "manufacturer": "HANSCHIP semiconductor",+    "package": "SOP-16",+    "pin_count": 16,+    "category": "Transistors/Thyristors",+    "subcategory": "Darlington Transistor Arrays",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590456765947928576",+    "parts": {+      "symbol": "uln2003cdrg.kicad_sym",+      "footprint": "uln2003cdrg.kicad_mod",+      "model_3d": "uln2003cdrg-etched.glb",+      "model_3d_plain": "uln2003cdrg.glb",+      "model_3d_step": "uln2003cdrg-etched.step",+      "model_3d_step_plain": "uln2003cdrg.step",+      "lbr": "uln2003cdrg.lbr"+    },+    "distributor_links": {+      "lcsc": "C5145405"+    },+    "distributor_check": {+      "checked_at": "2026-09-29T16:54:58Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": null,+        "status": "no match"+      },+      "mouser": {+        "pn": null,+        "status": "no match"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "IN1",+        "type": "input",+        "description": "Channel 1 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V."+      },+      {+        "number": "2",+        "name": "IN2",+        "type": "input",+        "description": "Channel 2 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V."+      },+      {+        "number": "3",+        "name": "IN3",+        "type": "input",+        "description": "Channel 3 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V."+      },+      {+        "number": "4",+        "name": "IN4",+        "type": "input",+        "description": "Channel 4 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V."+      },+      {+        "number": "5",+        "name": "IN5",+        "type": "input",+        "description": "Channel 5 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V."+      },+      {+        "number": "6",+        "name": "IN6",+        "type": "input",+        "description": "Channel 6 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V."+      },+      {+        "number": "7",+        "name": "IN7",+        "type": "input",+        "description": "Channel 7 Darlington base input; 2.7 kΩ series base resistor; TTL/CMOS compatible at V+ = 5 V; input voltage range −0.3 V to 30 V."+      },+      {+        "number": "8",+        "name": "GND",+        "type": "power_in",+        "description": "Common emitter return; all seven NPN Darlington pair emitters tied to this pin; connect to ground."+      },+      {+        "number": "9",+        "name": "COM",+        "type": "power_in",+        "description": "Common cathode of internal flyback suppression diodes; connect to inductive-load supply rail; withstands up to 50 V off-state."+      },+      {+        "number": "10",+        "name": "OUT7",+        "type": "output",+        "description": "Channel 7 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V."+      },+      {+        "number": "11",+        "name": "OUT6",+        "type": "output",+        "description": "Channel 6 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V."+      },+      {+        "number": "12",+        "name": "OUT5",+        "type": "output",+        "description": "Channel 5 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V."+      },+      {+        "number": "13",+        "name": "OUT4",+        "type": "output",+        "description": "Channel 4 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V."+      },+      {+        "number": "14",+        "name": "OUT3",+        "type": "output",+        "description": "Channel 3 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V."+      },+      {+        "number": "15",+        "name": "OUT2",+        "type": "output",+        "description": "Channel 2 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V."+      },+      {+        "number": "16",+        "name": "OUT1",+        "type": "output",+        "description": "Channel 1 open-collector output; max continuous collector current 500 mA; VCE(sat) max 1.6 V at IC = 350 mA; off-state voltage up to 50 V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590456765947928576",+        "pages": 8,+        "sha256": "97f33aca6df18240",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file