component
ULN2003AFWG
Public Made by Adomby adom
TOSHIBA Darlington Transistor Arrays, SOIC-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# ULN2003AFWG++**TOSHIBA** · Darlington Transistor Arrays · SOIC-16++ULN2003AFWG from TOSHIBA, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | I1 | input | Input channel 1 for Darlington pair 1; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |+| 2 | I2 | input | Input channel 2 for Darlington pair 2; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |+| 3 | I3 | input | Input channel 3 for Darlington pair 3; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |+| 4 | I4 | input | Input channel 4 for Darlington pair 4; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |+| 5 | I5 | input | Input channel 5 for Darlington pair 5; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |+| 6 | I6 | input | Input channel 6 for Darlington pair 6; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |+| 7 | I7 | input | Input channel 7 for Darlington pair 7; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |+| 8 | GND | power_in | Common emitter ground return for all seven NPN Darlington pairs; connect to system ground. |+| 9 | COMMON | passive | Clamp diode cathode bus; connect to inductive load supply (VCE(SUS) max 50 V, IF max 500 mA) for flyback suppression; may be left open when clamp diodes are not used. |+| 10 | O7 | tri_state | Open-collector NPN Darlington output channel 7 (paired with I7); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |+| 11 | O6 | tri_state | Open-collector NPN Darlington output channel 6 (paired with I6); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |+| 12 | O5 | tri_state | Open-collector NPN Darlington output channel 5 (paired with I5); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |+| 13 | O4 | tri_state | Open-collector NPN Darlington output channel 4 (paired with I4); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |+| 14 | O3 | tri_state | Open-collector NPN Darlington output channel 3 (paired with I3); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |+| 15 | O2 | tri_state | Open-collector NPN Darlington output channel 2 (paired with I2); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |+| 16 | O1 | tri_state | Open-collector NPN Darlington output channel 1 (paired with I1); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | TOSHIBA |+| Package | SOIC-16 |+| Category | Triode/MOS Tube/Transistor |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `ULN2003AFWG`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `uln2003afwg-etched.step` / `uln2003afwg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uln2003afwg.step` / `uln2003afwg.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [TOSHIBA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8579709723107004416) (11 pp, sha256 `117c2ac6e3d676f9`, retrieved 2026-09-29, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/uln2003afwg-datasheet.pdf)
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Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "triode-mos tube-transistor",+ "uln2003afwg",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "uln2003afwg.kicad_sym",+ "uln2003afwg.kicad_mod",+ "uln2003afwg.glb",+ "uln2003afwg.step",+ "uln2003afwg.lbr",+ "docs/hero.png",+ "docs/uln2003afwg-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ULN2003AFWG",+ "manufacturer": "TOSHIBA",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Triode/MOS Tube/Transistor",+ "subcategory": "Darlington Transistor Arrays",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8579709723107004416",+ "parts": {+ "symbol": "uln2003afwg.kicad_sym",+ "footprint": "uln2003afwg.kicad_mod",+ "model_3d": "uln2003afwg-etched.glb",+ "model_3d_plain": "uln2003afwg.glb",+ "model_3d_step": "uln2003afwg-etched.step",+ "model_3d_step_plain": "uln2003afwg.step",+ "lbr": "uln2003afwg.lbr"+ },+ "distributor_links": {+ "lcsc": "C5437"+ },+ "distributor_check": {+ "checked_at": "2026-09-29T16:59:36Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "I1",+ "type": "input",+ "description": "Input channel 1 for Darlington pair 1; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V."+ },+ {+ "number": "2",+ "name": "I2",+ "type": "input",+ "description": "Input channel 2 for Darlington pair 2; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V."+ },+ {+ "number": "3",+ "name": "I3",+ "type": "input",+ "description": "Input channel 3 for Darlington pair 3; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V."+ },+ {+ "number": "4",+ "name": "I4",+ "type": "input",+ "description": "Input channel 4 for Darlington pair 4; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V."+ },+ {+ "number": "5",+ "name": "I5",+ "type": "input",+ "description": "Input channel 5 for Darlington pair 5; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V."+ },+ {+ "number": "6",+ "name": "I6",+ "type": "input",+ "description": "Input channel 6 for Darlington pair 6; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V."+ },+ {+ "number": "7",+ "name": "I7",+ "type": "input",+ "description": "Input channel 7 for Darlington pair 7; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Common emitter ground return for all seven NPN Darlington pairs; connect to system ground."+ },+ {+ "number": "9",+ "name": "COMMON",+ "type": "passive",+ "description": "Clamp diode cathode bus; connect to inductive load supply (VCE(SUS) max 50 V, IF max 500 mA) for flyback suppression; may be left open when clamp diodes are not used."+ },+ {+ "number": "10",+ "name": "O7",+ "type": "tri_state",+ "description": "Open-collector NPN Darlington output channel 7 (paired with I7); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA."+ },+ {+ "number": "11",+ "name": "O6",+ "type": "tri_state",+ "description": "Open-collector NPN Darlington output channel 6 (paired with I6); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA."+ },+ {+ "number": "12",+ "name": "O5",+ "type": "tri_state",+ "description": "Open-collector NPN Darlington output channel 5 (paired with I5); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA."+ },+ {+ "number": "13",+ "name": "O4",+ "type": "tri_state",+ "description": "Open-collector NPN Darlington output channel 4 (paired with I4); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA."+ },+ {+ "number": "14",+ "name": "O3",+ "type": "tri_state",+ "description": "Open-collector NPN Darlington output channel 3 (paired with I3); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA."+ },+ {+ "number": "15",+ "name": "O2",+ "type": "tri_state",+ "description": "Open-collector NPN Darlington output channel 2 (paired with I2); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA."+ },+ {+ "number": "16",+ "name": "O1",+ "type": "tri_state",+ "description": "Open-collector NPN Darlington output channel 1 (paired with I1); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8579709723107004416",+ "pages": 11,+ "sha256": "117c2ac6e3d676f9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}