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Initial commit: component/ucc38c40dr

Ray ·a6d878267f ·1d ago
2 files changed +241
README.mdadded+44
@@ -0,0 +1,44 @@+# UCC38C40DR++**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-8++UCC38C40DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | COMP | output | Error amplifier compensation output; internally current-limited and can be forced to GND to command zero duty cycle. |+| 2 | FB | input | Inverting input to error amplifier for feedback loop stability; compared against 2.5V ± 1% internally-trimmed noninverting input. |+| 3 | CS | input | Current sense input to PWM comparator; signal compared to error amplifier output to control switch conduction. |+| 4 | RT/CT | bidirectional | Oscillator timing node; connect timing resistor to VREF and timing capacitor to GND to set switching frequency. |+| 5 | GND | power_in | Ground return pin for output driver stage and logic level controller section. |+| 6 | OUT | output | Gate driver output capable of sourcing and sinking 1A peak current; actively held low when VDD is below turn-on threshold. |+| 7 | VDD | power_in | Analog controller bias and power input requiring 0.1µF bypass capacitor to GND with minimal trace length. |+| 8 | VREF | power_out | 5V reference voltage output with ±1% accuracy for oscillator timing and internal biasing; requires 0.1µF ceramic bypass to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-8 |+| Category | Power Management (PMIC) |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `UCC38C40DR`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)+- 3D model files: `ucc38c40dr-etched.step` / `ucc38c40dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc38c40dr.step` / `ucc38c40dr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc38c40.pdf) (60 pp, sha256 `9fa55f996731c56b`, retrieved 2026-10-07, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ucc38c40dr-datasheet.pdf)
page.jsonadded+197
@@ -0,0 +1,197 @@+{+  "slug": "ucc38c40dr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "ucc38c40dr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ucc38c40dr.kicad_sym",+    "ucc38c40dr.kicad_mod",+    "ucc38c40dr.glb",+    "ucc38c40dr.step",+    "ucc38c40dr.lbr",+    "docs/hero.png",+    "docs/ucc38c40dr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "ucc38c40dr-hero.glb",+    "ucc38c40dr-hero.overlay.json"+  ],+  "component": {+    "mpn": "UCC38C40DR",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "Power Management (PMIC)",+    "subcategory": "AC-DC Controllers And Regulators",+    "datasheet": "https://www.ti.com/lit/ds/symlink/ucc38c40.pdf",+    "parts": {+      "symbol": "ucc38c40dr.kicad_sym",+      "footprint": "ucc38c40dr.kicad_mod",+      "model_3d": "ucc38c40dr-hero.glb",+      "model_3d_plain": "ucc38c40dr.glb",+      "model_3d_step": "ucc38c40dr-etched.step",+      "model_3d_step_plain": "ucc38c40dr.step",+      "lbr": "ucc38c40dr.lbr"+    },+    "distributor_links": {+      "lcsc": "C7124",+      "digikey": "296-UCC38C40DRTR-ND",+      "mouser": "595-UCC38C40DR"+    },+    "distributor_check": {+      "checked_at": "2026-10-07T01:31:29Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-UCC38C40DRTR-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-UCC38C40DR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "COMP",+        "type": "output",+        "description": "Error amplifier compensation output; internally current-limited and can be forced to GND to command zero duty cycle."+      },+      {+        "number": "2",+        "name": "FB",+        "type": "input",+        "description": "Inverting input to error amplifier for feedback loop stability; compared against 2.5V ± 1% internally-trimmed noninverting input."+      },+      {+        "number": "3",+        "name": "CS",+        "type": "input",+        "description": "Current sense input to PWM comparator; signal compared to error amplifier output to control switch conduction."+      },+      {+        "number": "4",+        "name": "RT/CT",+        "type": "bidirectional",+        "description": "Oscillator timing node; connect timing resistor to VREF and timing capacitor to GND to set switching frequency."+      },+      {+        "number": "5",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin for output driver stage and logic level controller section."+      },+      {+        "number": "6",+        "name": "OUT",+        "type": "output",+        "description": "Gate driver output capable of sourcing and sinking 1A peak current; actively held low when VDD is below turn-on threshold."+      },+      {+        "number": "7",+        "name": "VDD",+        "type": "power_in",+        "description": "Analog controller bias and power input requiring 0.1µF bypass capacitor to GND with minimal trace length."+      },+      {+        "number": "8",+        "name": "VREF",+        "type": "power_out",+        "description": "5V reference voltage output with ±1% accuracy for oscillator timing and internal biasing; requires 0.1µF ceramic bypass to GND."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 15,+        "cost_usd": 0.1416,+        "at": "2026-10-07T01:31:15"+      },+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/ucc38c40.pdf",+        "pages": 60,+        "sha256": "9fa55f996731c56b",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "ucc38c40dr.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          4.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "ucc38c40dr-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          4.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "231eabc5d60bc3f03b28b7a351932ec389e7509fd9a0464220c23adf413b1f27",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file