UCC28C43DR

@@ -26,7 +26,10 @@       "model_3d_step": "ucc28c43dr.step",       "lbr": "ucc28c43dr.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "digikey": "296-27164-2-ND",+      "lcsc": "C111694"+    },     "pins": [       {         "number": "1",@@ -38,19 +41,19 @@         "number": "2",         "name": "FB",         "type": "input",-        "description": "Inverting input to the internal error amplifier used to control the power converter voltage-feedback loop for stability. The non-inverting input is internally trimmed to 2.5V ± 1%."+        "description": "Inverting input to the internal error amplifier used to control the power converter voltage-feedback loop for stability. The non-inverting input is internally trimmed to 2.5V \u00b1 1%."       },       {         "number": "3",         "name": "CS",         "type": "input",-        "description": "Primary-side current sense input (non-inverting input to the PWM comparator). Connect to the current-sense resistor; when this signal exceeds the scaled error-amplifier voltage the PWM terminates OUT conduction. A voltage ramp may be applied here for voltage-mode operation. COMP-to-CS offset ≈ 1.15V, max CS input signal ≈ 1V."+        "description": "Primary-side current sense input (non-inverting input to the PWM comparator). Connect to the current-sense resistor; when this signal exceeds the scaled error-amplifier voltage the PWM terminates OUT conduction. A voltage ramp may be applied here for voltage-mode operation. COMP-to-CS offset \u2248 1.15V, max CS input signal \u2248 1V."       },       {         "number": "4",         "name": "RT/CT",         "type": "bidirectional",-        "description": "Fixed-frequency oscillator timing node. Connect timing resistor R_RT from VREF to this pin and timing capacitor C_CT from this pin to GND to set switching frequency (fSW = fOSC for the C43). Peak-to-peak ramp ≈ 1.9V; internal discharge current ≈ 8.4mA (with R_RT = 10kΩ)."+        "description": "Fixed-frequency oscillator timing node. Connect timing resistor R_RT from VREF to this pin and timing capacitor C_CT from this pin to GND to set switching frequency (fSW = fOSC for the C43). Peak-to-peak ramp \u2248 1.9V; internal discharge current \u2248 8.4mA (with R_RT = 10k\u03a9)."       },       {         "number": "5",@@ -62,19 +65,19 @@         "number": "6",         "name": "OUT",         "type": "output",-        "description": "High-current totem-pole gate-drive output intended to directly drive an external MOSFET gate. Rail-to-rail ±1A peak (source/sink), 25ns rise / 20ns fall into 1nF; runs at the oscillator frequency with up to ~100% duty cycle for the UCC28C43. OUT is actively held low when VDD is below the turn-on threshold."+        "description": "High-current totem-pole gate-drive output intended to directly drive an external MOSFET gate. Rail-to-rail \u00b11A peak (source/sink), 25ns rise / 20ns fall into 1nF; runs at the oscillator frequency with up to ~100% duty cycle for the UCC28C43. OUT is actively held low when VDD is below the turn-on threshold."       },       {         "number": "7",         "name": "VDD",         "type": "power_in",-        "description": "Analog controller bias supply input (recommended operating range up to 18V, absolute max 20V). Requires a 0.1µF bypass to GND with minimal trace length and additional bulk capacitance ≥ 10× the external MOSFET gate capacitance. UVLO turn-on 8.4V / turn-off 7.6V (C43 variant); startup current 50µA typ, operating current 2.3mA typ."+        "description": "Analog controller bias supply input (recommended operating range up to 18V, absolute max 20V). Requires a 0.1\u00b5F bypass to GND with minimal trace length and additional bulk capacitance \u2265 10\u00d7 the external MOSFET gate capacitance. UVLO turn-on 8.4V / turn-off 7.6V (C43 variant); startup current 50\u00b5A typ, operating current 2.3mA typ."       },       {         "number": "8",         "name": "VREF",         "type": "power_out",-        "description": "5V ±1% precision reference output used to source oscillator timing current through R_RT and to power light external loads (up to 20mA source). Must be bypassed to GND with at least a 0.1µF ceramic located close to the pin for stability."+        "description": "5V \u00b11% precision reference output used to source oscillator timing current through R_RT and to power light external loads (up to 20mA source). Must be bypassed to GND with at least a 0.1\u00b5F ceramic located close to the pin for stability."       }     ],     "provenance": {

@@ -62,6 +62,18 @@   <smd name="6" x="2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-2.6000" y="2.4700"/>+    <vertex x="-2.8400" y="2.8000"/>+    <vertex x="-2.3600" y="2.8000"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.9750" y="2.4500"/>+    <vertex x="1.9500" y="2.4500"/>+    <vertex x="1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="1.4750"/>+  </polygon>   <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -70,7 +82,7 @@   <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/>   <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="UCC28C43DR">@@ -108,7 +120,14 @@         <connect gate="G$1" pin="OUT" pad="6"/>         <connect gate="G$1" pin="GND" pad="5"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="UCC28C43DR" constant="no"/>+          <attribute name="MANUFACTURER" value="Texas Instruments" constant="no"/>+          <attribute name="DIGIKEY_PN" value="296-27164-2-ND" constant="no"/>+          <attribute name="LCSC_PN" value="C111694" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>