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Set visibility: public

Ray ·2f2457a843 ·9d ago ·parent 1b31b46
1 file changed +7−4
page.json+7−4
@@ -64,19 +64,19 @@         "number": "3",         "name": "ENBL",         "type": "input",-        "description": "Enable input with logic compatible threshold and hysteresis, internally pulled up to VDD with 100-k\u03a9 resistor for active high operation, controlling driver output enable/disable state."+        "description": "Enable input with logic compatible threshold and hysteresis, internally pulled up to VDD with 100-kΩ resistor for active high operation, controlling driver output enable/disable state."       },       {         "number": "4",         "name": "AGND",         "type": "power_in",-        "description": "Analog ground for input stage that must be connected to Pin 5 via single thick trace directly under the device, with 0.1-\u00b5F bypass capacitor to VDD (Pin 1)."+        "description": "Analog ground for input stage that must be connected to Pin 5 via single thick trace directly under the device, with 0.1-µF bypass capacitor to VDD (Pin 1)."       },       {         "number": "5",         "name": "PGND",         "type": "power_in",-        "description": "Power ground for output stage that must be connected directly to the source of the power MOSFET and to Pin 4 via single thick trace, with 0.1-\u00b5F bypass capacitor to VDD (Pin 8)."+        "description": "Power ground for output stage that must be connected directly to the source of the power MOSFET and to Pin 4 via single thick trace, with 0.1-µF bypass capacitor to VDD (Pin 8)."       },       {         "number": "6",@@ -172,5 +172,8 @@     "docs/ucc27322dr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file