component
UCC21521CDWR
Public Made by Adomby adom
Texas Instruments Isolators - Gate Drivers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# UCC21521CDWR++**Texas Instruments** · Isolators - Gate Drivers · SOIC-16-300mil++UCC21521CDWR from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | INA | input | Input signal for the A channel with a TTL/CMOS compatible threshold; the pin is pulled low internally if left open and should be tied to ground if unused. |+| 2 | INB | input | Input signal for the B channel with a TTL/CMOS compatible threshold; the pin is pulled low internally if left open and should be tied to ground if unused. |+| 3 | VCCI | power_in | Primary-side supply voltage (3 V to 18 V recommended range), locally decoupled to GND with a low ESR/ESL capacitor placed as close to the device as possible. |+| 4 | GND | power_in | Primary-side ground reference; all primary-side signals are referenced to this pin. |+| 5 | EN | input | Enables both driver outputs when high or left open (internally pulled high) and disables the outputs when low; tying it to VCCI is recommended for better noise immunity when unused. |+| 6 | DT | input | Programmable dead-time pin: tying it to VCCI allows overlap, while a 500 Ω to 500 kΩ resistor to GND sets dead time as DT (ns) = 10 × RDT (kΩ), with a ceramic capacitor of 2.2 nF or above recommended in parallel; leaving it floating is not recommended. |+| 7 | NC | unconnected | No internal connection. |+| 8 | VCCI | power_in | Primary-side supply voltage, internally shorted to pin 3 (VCCI), so it should be connected and decoupled alongside pin 3. |+| 9 | VSSB | power_in | Ground for the secondary-side driver B and its ground reference for the B channel. |+| 10 | OUTB | output | Output of driver B; connect to the gate of the B-channel FET or IGBT. |+| 11 | VDDB | power_in | Secondary-side power for driver B, to be locally decoupled to VSSB with a low ESR/ESL capacitor placed as close to the device as possible. |+| 12 | NC | unconnected | No internal connection. |+| 13 | NC | unconnected | No internal connection. |+| 14 | VSSA | power_in | Ground for secondary-side driver A and its ground reference for the A channel. |+| 15 | OUTA | output | Output of driver A; connect to the gate of the A-channel FET or IGBT. |+| 16 | VDDA | power_in | Secondary-side power for driver A, to be locally decoupled to VSSA with a low ESR/ESL capacitor placed as close to the device as possible. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16-300mil |+| Category | Power Management (PMIC) |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `UCC21521CDWR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)+- 3D model files: `ucc21521cdwr-etched.step` / `ucc21521cdwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc21521cdwr.step` / `ucc21521cdwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ucc21521) (50 pp, sha256 `93b1d040e8ae41ee`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ucc21521cdwr-datasheet.pdf)
page.jsonadded+247@@ -0,0 +1,247 @@+{+ "slug": "ucc21521cdwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Isolators - Gate Drivers, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "ucc21521cdwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ucc21521cdwr.kicad_sym",+ "ucc21521cdwr.kicad_mod",+ "ucc21521cdwr.glb",+ "ucc21521cdwr.step",+ "ucc21521cdwr.lbr",+ "docs/hero.png",+ "docs/ucc21521cdwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ucc21521cdwr-hero.glb",+ "ucc21521cdwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "UCC21521CDWR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16-300mil",+ "pin_count": 16,+ "category": "Power Management (PMIC)",+ "subcategory": "Isolators - Gate Drivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/ucc21521",+ "parts": {+ "symbol": "ucc21521cdwr.kicad_sym",+ "footprint": "ucc21521cdwr.kicad_mod",+ "model_3d": "ucc21521cdwr-hero.glb",+ "model_3d_plain": "ucc21521cdwr.glb",+ "model_3d_step": "ucc21521cdwr-etched.step",+ "model_3d_step_plain": "ucc21521cdwr.step",+ "lbr": "ucc21521cdwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C189707",+ "digikey": "296-47680-2-ND",+ "mouser": "595-UCC21521CDWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T21:41:42Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-47680-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-UCC21521CDWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "INA",+ "type": "input",+ "description": "Input signal for the A channel with a TTL/CMOS compatible threshold; the pin is pulled low internally if left open and should be tied to ground if unused."+ },+ {+ "number": "2",+ "name": "INB",+ "type": "input",+ "description": "Input signal for the B channel with a TTL/CMOS compatible threshold; the pin is pulled low internally if left open and should be tied to ground if unused."+ },+ {+ "number": "3",+ "name": "VCCI",+ "type": "power_in",+ "description": "Primary-side supply voltage (3 V to 18 V recommended range), locally decoupled to GND with a low ESR/ESL capacitor placed as close to the device as possible."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Primary-side ground reference; all primary-side signals are referenced to this pin."+ },+ {+ "number": "5",+ "name": "EN",+ "type": "input",+ "description": "Enables both driver outputs when high or left open (internally pulled high) and disables the outputs when low; tying it to VCCI is recommended for better noise immunity when unused."+ },+ {+ "number": "6",+ "name": "DT",+ "type": "input",+ "description": "Programmable dead-time pin: tying it to VCCI allows overlap, while a 500 Ω to 500 kΩ resistor to GND sets dead time as DT (ns) = 10 × RDT (kΩ), with a ceramic capacitor of 2.2 nF or above recommended in parallel; leaving it floating is not recommended."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "8",+ "name": "VCCI",+ "type": "power_in",+ "description": "Primary-side supply voltage, internally shorted to pin 3 (VCCI), so it should be connected and decoupled alongside pin 3."+ },+ {+ "number": "9",+ "name": "VSSB",+ "type": "power_in",+ "description": "Ground for the secondary-side driver B and its ground reference for the B channel."+ },+ {+ "number": "10",+ "name": "OUTB",+ "type": "output",+ "description": "Output of driver B; connect to the gate of the B-channel FET or IGBT."+ },+ {+ "number": "11",+ "name": "VDDB",+ "type": "power_in",+ "description": "Secondary-side power for driver B, to be locally decoupled to VSSB with a low ESR/ESL capacitor placed as close to the device as possible."+ },+ {+ "number": "12",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "13",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "14",+ "name": "VSSA",+ "type": "power_in",+ "description": "Ground for secondary-side driver A and its ground reference for the A channel."+ },+ {+ "number": "15",+ "name": "OUTA",+ "type": "output",+ "description": "Output of driver A; connect to the gate of the A-channel FET or IGBT."+ },+ {+ "number": "16",+ "name": "VDDA",+ "type": "power_in",+ "description": "Secondary-side power for driver A, to be locally decoupled to VSSA with a low ESR/ESL capacitor placed as close to the device as possible."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout taken from the DW 16-pin SOIC top-view figure and Table 5-1 (page 3). The DW package is the o; Pin 3 and pin 8 are both VCCI; pin 8 is internally shorted to pin 3 per the datasheet, so both are l"+ ],+ "pages_sent": 14,+ "cost_usd": 0.0861,+ "at": "2026-10-07T21:41:20"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ucc21521",+ "pages": 50,+ "sha256": "93b1d040e8ae41ee",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ucc21521cdwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ucc21521cdwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d76f4f4bb3604b394e787e3f9a17057857a11218e716f60bc1c0944436a065ff",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}