component
UC3845D8TR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+45@@ -0,0 +1,45 @@+# UC3845D8TR++**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-8++UC3845D8TR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | COMP | output | Error amplifier output and compensation pin; the open-collector error amplifier has internal current limiting, so COMP can be forced to GROUND to obtain zero duty cycle. |+| 2 | VFB | input | Inverting input of the internal error amplifier used for voltage feedback loop control; keep the VFB trace as short as possible with minimal stray capacitance for stability. |+| 3 | ISENSE | input | Primary-side current sense input to the PWM comparator that terminates OUTPUT conduction; the typical ISENSE voltage is 1 V, with a maximum input voltage of 1 V. |+| 4 | RT/CT | bidirectional | Oscillator timing pin: RT connects from VREF and CT to GROUND to set the switching frequency via fOSC = 1.72/(RT x CT), and RT must never be smaller than 5 kΩ. |+| 5 | GROUND | power_in | Combined signal (analog) and power ground for this 8-pin package, which has no separate PWRGND pin; keep the timing capacitor and bypass returns on a single point ground. |+| 6 | OUTPUT | output | Totem-pole gate driver output that drives the external MOSFET directly, sourcing and sinking peak current up to 1 A, and held low when VCC is below the turn-on threshold. |+| 7 | VCC | power_in | Power supply input for the controller, with recommended supply voltage 12 V to 28 V, absolute maximum 30 V from a low-impedance source, and a bypass capacitor of typically 0.1 µF to GROUND placed close to the pin. |+| 8 | VREF | power_out | 5 V reference output that must be bypassed to GROUND with a ceramic capacitor of at least 0.1 µF placed close to the pin, and external loads on VREF require additional bypassing. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-8 |+| Category | Power Management (PMIC) |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `UC3845D8TR`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)+- 3D model files: `uc3845d8tr-etched.step` / `uc3845d8tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uc3845d8tr.step` / `uc3845d8tr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/uc2843) (61 pp, sha256 `0f875fd24cbb5fda`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/uc3845d8tr-datasheet.pdf)
page.jsonadded+200@@ -0,0 +1,200 @@+{+ "slug": "uc3845d8tr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "uc3845d8tr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "uc3845d8tr.kicad_sym",+ "uc3845d8tr.kicad_mod",+ "uc3845d8tr.glb",+ "uc3845d8tr.step",+ "uc3845d8tr.lbr",+ "docs/hero.png",+ "docs/uc3845d8tr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "uc3845d8tr-hero.glb",+ "uc3845d8tr-hero.overlay.json"+ ],+ "component": {+ "mpn": "UC3845D8TR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-8",+ "pin_count": 8,+ "category": "Power Management (PMIC)",+ "subcategory": "AC-DC Controllers And Regulators",+ "datasheet": "https://www.ti.com/cn/lit/gpn/uc2843",+ "parts": {+ "symbol": "uc3845d8tr.kicad_sym",+ "footprint": "uc3845d8tr.kicad_mod",+ "model_3d": "uc3845d8tr-hero.glb",+ "model_3d_plain": "uc3845d8tr.glb",+ "model_3d_step": "uc3845d8tr-etched.step",+ "model_3d_step_plain": "uc3845d8tr.step",+ "lbr": "uc3845d8tr.lbr"+ },+ "distributor_links": {+ "lcsc": "C523771",+ "digikey": "296-38313-2-ND",+ "mouser": "595-UC3845D8TR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T03:21:15Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-38313-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-UC3845D8TR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "COMP",+ "type": "output",+ "description": "Error amplifier output and compensation pin; the open-collector error amplifier has internal current limiting, so COMP can be forced to GROUND to obtain zero duty cycle."+ },+ {+ "number": "2",+ "name": "VFB",+ "type": "input",+ "description": "Inverting input of the internal error amplifier used for voltage feedback loop control; keep the VFB trace as short as possible with minimal stray capacitance for stability."+ },+ {+ "number": "3",+ "name": "ISENSE",+ "type": "input",+ "description": "Primary-side current sense input to the PWM comparator that terminates OUTPUT conduction; the typical ISENSE voltage is 1 V, with a maximum input voltage of 1 V."+ },+ {+ "number": "4",+ "name": "RT/CT",+ "type": "bidirectional",+ "description": "Oscillator timing pin: RT connects from VREF and CT to GROUND to set the switching frequency via fOSC = 1.72/(RT x CT), and RT must never be smaller than 5 kΩ."+ },+ {+ "number": "5",+ "name": "GROUND",+ "type": "power_in",+ "description": "Combined signal (analog) and power ground for this 8-pin package, which has no separate PWRGND pin; keep the timing capacitor and bypass returns on a single point ground."+ },+ {+ "number": "6",+ "name": "OUTPUT",+ "type": "output",+ "description": "Totem-pole gate driver output that drives the external MOSFET directly, sourcing and sinking peak current up to 1 A, and held low when VCC is below the turn-on threshold."+ },+ {+ "number": "7",+ "name": "VCC",+ "type": "power_in",+ "description": "Power supply input for the controller, with recommended supply voltage 12 V to 28 V, absolute maximum 30 V from a low-impedance source, and a bypass capacitor of typically 0.1 µF to GROUND placed close to the pin."+ },+ {+ "number": "8",+ "name": "VREF",+ "type": "power_out",+ "description": "5 V reference output that must be bypassed to GROUND with a ceramic capacitor of at least 0.1 µF placed close to the pin, and external loads on VREF require additional bypassing."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin numbers, names and the 8-pin assignment come from the Table 5-1 column for SOIC/CDIP/PDIP (8) an; The datasheet lists VCC as type I and VREF as type O. I mapped VCC to power_in and VREF to power_out; The datasheet lists COMP as type O, but the pin also sinks and sources current and is used as a feed"+ ],+ "pages_sent": 38,+ "cost_usd": 0.2239,+ "at": "2026-10-08T03:20:58"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/uc2843",+ "pages": 61,+ "sha256": "0f875fd24cbb5fda",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "uc3845d8tr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 4.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "uc3845d8tr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 4.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f5b635d088b20327144aa3e72a0de28770ec8e0ad6c9090989338f0b3f86ef9b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}