component
UC2875DWPTR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+64@@ -0,0 +1,64 @@+# UC2875DWPTR++**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-28-300mil++UC2875DWPTR from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VREF | power_out | Accurate 5V reference output delivering about 60mA, short-circuit limited, disabled in UVLO, bypass with a 0.1µF low-ESR capacitor to GND. |+| 2 | E/AOUT | output | Error amplifier output and gain stage for overall feedback control; levels below 1V force 0° phase shift. |+| 3 | EA- | input | Error amplifier inverting input, normally connected to the divider sensing the power supply output voltage. |+| 4 | EA+ | input | Error amplifier non-inverting input, normally connected to a reference voltage for comparison with the sensed output level. |+| 5 | CS+ | input | Non-inverting input of the current-fault comparator with internal 2.5V reference; exceeding 2.5V latches outputs off and starts a soft-start cycle. |+| 6 | SOFTSTART | output | Soft-start pin held at GND while VIN is below UVLO, then pulled up to about 4.8V by an internal 9µA source. |+| 7 | GND | power_in | Signal ground, reference for all voltages. |+| 8 | GND | power_in | Signal ground, reference for all voltages. |+| 9 | GND | power_in | Signal ground, reference for all voltages. |+| 10 | DELAYSET C-D | input | Programmed current from this pin to GND sets the turn-on delay for the C-D output pair. |+| 11 | N/C | unconnected | No connection. |+| 12 | OUTD | output | 2A totem-pole output D, part of the C-D pair driving the second half-bridge phase-shifted from A-B. |+| 13 | OUTC | output | 2A totem-pole output C, part of the C-D pair driving the second half-bridge phase-shifted from A-B. |+| 14 | VC | power_in | Supply for the output drivers; connect to a stable source above 3V (above 12V for best performance), bypassed to PWRGND. |+| 15 | VIN | power_in | Primary chip supply for logic and analog circuitry; connect to a stable source above 12V, inactive until VIN exceeds the UVLO threshold, bypass to GND. |+| 16 | PWRGND | power_in | Power ground for the output drivers; bypass VC to it with a ceramic capacitor, may be joined to signal ground at a single point. |+| 17 | OUTB | output | 2A totem-pole output B, part of the A-B pair driving one half-bridge synchronized with the clock. |+| 18 | OUTA | output | 2A totem-pole output A, part of the A-B pair driving one half-bridge synchronized with the clock. |+| 19 | N/C | unconnected | No connection. |+| 20 | GND | power_in | Signal ground, reference for all voltages. |+| 21 | GND | power_in | Signal ground, reference for all voltages. |+| 22 | GND | power_in | Signal ground, reference for all voltages. |+| 23 | DELAYSET A-B | input | Programmed current from this pin to GND sets the turn-on delay for the A-B output pair. |+| 24 | FREQSET | passive | A resistor and capacitor from this pin to GND set the oscillator frequency. |+| 25 | CLOCKSYNC | bidirectional | Outputs a clock signal or accepts a synchronization input higher in frequency than the local oscillator. |+| 26 | SLOPE | passive | A resistor from this pin to VCC sets the current used to generate the ramp, giving slope compensation or voltage feed-forward. |+| 27 | RAMP | input | Input to the PWM comparator; connect a capacitor to GND, with 1.3V offset between ramp input and PWM comparator. |+| 28 | GND | power_in | Signal ground, reference for all voltages. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-28-300mil |+| Category | Power Management (PMIC) |+| Pins | 28 |++## CAD (KiCad official)++- Symbol: `UC2875DWPTR`+- Footprint: `Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm`+- 3D model: SOIC-28-300mil (KiCad packages3D, STEP)+- 3D model files: `uc2875dwptr-etched.step` / `uc2875dwptr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uc2875dwptr.step` / `uc2875dwptr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/uc2875) (23 pp, sha256 `4544bfc895c90421`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/uc2875dwptr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "uc2875dwptr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "uc2875dwptr.kicad_sym",+ "uc2875dwptr.kicad_mod",+ "uc2875dwptr.glb",+ "uc2875dwptr.step",+ "uc2875dwptr.lbr",+ "docs/hero.png",+ "docs/uc2875dwptr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "uc2875dwptr-hero.glb",+ "uc2875dwptr-hero.overlay.json"+ ],+ "component": {+ "mpn": "UC2875DWPTR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-28-300mil",+ "pin_count": 28,+ "category": "Power Management (PMIC)",+ "subcategory": "AC-DC Controllers And Regulators",+ "datasheet": "https://www.ti.com/cn/lit/gpn/uc2875",+ "parts": {+ "symbol": "uc2875dwptr.kicad_sym",+ "footprint": "uc2875dwptr.kicad_mod",+ "model_3d": "uc2875dwptr-hero.glb",+ "model_3d_plain": "uc2875dwptr.glb",+ "model_3d_step": "uc2875dwptr-etched.step",+ "model_3d_step_plain": "uc2875dwptr.step",+ "lbr": "uc2875dwptr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2868119",+ "digikey": "UC2875DWPTR-ND",+ "mouser": "595-UC2875DWPTR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T07:25:46Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "UC2875DWPTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-UC2875DWPTR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VREF",+ "type": "power_out",+ "description": "Accurate 5V reference output delivering about 60mA, short-circuit limited, disabled in UVLO, bypass with a 0.1µF low-ESR capacitor to GND."+ },+ {+ "number": "2",+ "name": "E/AOUT",+ "type": "output",+ "description": "Error amplifier output and gain stage for overall feedback control; levels below 1V force 0° phase shift."+ },+ {+ "number": "3",+ "name": "EA-",+ "type": "input",+ "description": "Error amplifier inverting input, normally connected to the divider sensing the power supply output voltage."+ },+ {+ "number": "4",+ "name": "EA+",+ "type": "input",+ "description": "Error amplifier non-inverting input, normally connected to a reference voltage for comparison with the sensed output level."+ },+ {+ "number": "5",+ "name": "CS+",+ "type": "input",+ "description": "Non-inverting input of the current-fault comparator with internal 2.5V reference; exceeding 2.5V latches outputs off and starts a soft-start cycle."+ },+ {+ "number": "6",+ "name": "SOFTSTART",+ "type": "output",+ "description": "Soft-start pin held at GND while VIN is below UVLO, then pulled up to about 4.8V by an internal 9µA source."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground, reference for all voltages."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground, reference for all voltages."+ },+ {+ "number": "9",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground, reference for all voltages."+ },+ {+ "number": "10",+ "name": "DELAYSET C-D",+ "type": "input",+ "description": "Programmed current from this pin to GND sets the turn-on delay for the C-D output pair."+ },+ {+ "number": "11",+ "name": "N/C",+ "type": "unconnected",+ "description": "No connection."+ },+ {+ "number": "12",+ "name": "OUTD",+ "type": "output",+ "description": "2A totem-pole output D, part of the C-D pair driving the second half-bridge phase-shifted from A-B."+ },+ {+ "number": "13",+ "name": "OUTC",+ "type": "output",+ "description": "2A totem-pole output C, part of the C-D pair driving the second half-bridge phase-shifted from A-B."+ },+ {+ "number": "14",+ "name": "VC",+ "type": "power_in",+ "description": "Supply for the output drivers; connect to a stable source above 3V (above 12V for best performance), bypassed to PWRGND."+ },+ {+ "number": "15",+ "name": "VIN",+ "type": "power_in",+ "description": "Primary chip supply for logic and analog circuitry; connect to a stable source above 12V, inactive until VIN exceeds the UVLO threshold, bypass to GND."+ },+ {+ "number": "16",+ "name": "PWRGND",+ "type": "power_in",+ "description": "Power ground for the output drivers; bypass VC to it with a ceramic capacitor, may be joined to signal ground at a single point."+ },+ {+ "number": "17",+ "name": "OUTB",+ "type": "output",+ "description": "2A totem-pole output B, part of the A-B pair driving one half-bridge synchronized with the clock."+ },+ {+ "number": "18",+ "name": "OUTA",+ "type": "output",+ "description": "2A totem-pole output A, part of the A-B pair driving one half-bridge synchronized with the clock."+ },+ {+ "number": "19",+ "name": "N/C",+ "type": "unconnected",+ "description": "No connection."+ },+ {+ "number": "20",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground, reference for all voltages."+ },+ {+ "number": "21",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground, reference for all voltages."+ },+ {+ "number": "22",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground, reference for all voltages."+ },+ {+ "number": "23",+ "name": "DELAYSET A-B",+ "type": "input",+ "description": "Programmed current from this pin to GND sets the turn-on delay for the A-B output pair."+ },+ {+ "number": "24",+ "name": "FREQSET",+ "type": "passive",+ "description": "A resistor and capacitor from this pin to GND set the oscillator frequency."+ },+ {+ "number": "25",+ "name": "CLOCKSYNC",+ "type": "bidirectional",+ "description": "Outputs a clock signal or accepts a synchronization input higher in frequency than the local oscillator."+ },+ {+ "number": "26",+ "name": "SLOPE",+ "type": "passive",+ "description": "A resistor from this pin to VCC sets the current used to generate the ramp, giving slope compensation or voltage feed-forward."+ },+ {+ "number": "27",+ "name": "RAMP",+ "type": "input",+ "description": "Input to the PWM comparator; connect a capacitor to GND, with 1.3V offset between ramp input and PWM comparator."+ },+ {+ "number": "28",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground, reference for all voltages."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Datasheet describes GND once for all GND pins; description reused for each of the six-plus GND pins.; N/C pins labelled only in the connection diagram; the 28-pin SOIC diagram is shared across UC1875/6/",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 12,+ "cost_usd": 0.4186,+ "at": "2026-10-07T07:25:08"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/uc2875",+ "pages": 23,+ "sha256": "4544bfc895c90421",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 28,+ "described": 28,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "uc2875dwptr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 17.9,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b889a13dbe9ec59e79fa9f1b5118b00bfa54f9582392335ff3365b64afc264b1",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "uc2875dwptr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 17.9,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2c9e75d69828770890592e5f525034706b38a36a427922b6106a925d7fc868e",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}