component
TX41601
Public Made by Adomby adom
XDS DC-DC Converters, ETSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+58@@ -0,0 +1,58 @@+# TX41601++**XDS** · DC-DC Converters · ETSSOP-20++TX41601 from XDS, in a ETSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | EN | input | Enable pin: the part is enabled when EN is pulled above 1.2 V and enters shutdown when pulled below 1.0 V, with EN absolute maximum of 100 V to GND. |+| 2 | OVLO | input | Overvoltage lockout input, driven from an external divider to set the input overvoltage threshold; when OVLO is pulled above 1.2 V the controller is disabled and does not resume switching until EN is toggled. |+| 3 | OCSET | passive | Current-limit set point: a resistor from this pin to GND sets the positive and negative cycle-by-cycle current-limit thresholds, with OCSET rated to 6 V absolute maximum. |+| 4 | RON | passive | Switching frequency set: a resistor from this pin to GND programs the switching frequency over 50 kHz to 500 kHz, with RON rated to 6 V absolute maximum. |+| 5 | TOFF | input | Programmable shutdown delay: tie to GND for no delay, leave floating for 10 s, or tie to VCC for 20 s; TOFF absolute maximum is 12 V to GND. |+| 6 | SS | passive | Soft-start: an external capacitor from this pin to GND sets the output start-up time, with SS rated to 6 V absolute maximum. |+| 7 | AGND | power_in | Signal ground for the internal reference and control circuitry. |+| 8 | COMP | passive | Error amplifier output: an external resistor and capacitor network is normally connected from this pin to GND to provide loop compensation, with COMP rated to 6 V absolute maximum. |+| 9 | FB | input | Feedback input sensing the output voltage through a resistor divider from output to GND; FB is a sensitive node that should be kept away from SW and BST, and is rated to 6 V absolute maximum. |+| 10 | EXTVCC | power_in | External supply input for the internal VCC LDO; it bypasses the NDRV LDO when above 10 V, must not exceed 30 V or be connected above VIN, and should be tied to GND if unused. |+| 11 | ISNS2 | input | Inductor current sense input 2 (absolute maximum -0.3 V to 65 V to GND, recommended up to 60 V). |+| 12 | ISNS1 | input | Inductor current sense input 1 (absolute maximum -0.3 V to 65 V to GND, recommended up to 60 V). |+| 13 | NDRV | output | Gate drive output for the external pass device (NMOS or NPN) of the VCC NDRV LDO regulator. |+| 14 | VDD | power_out | Internal supply rail for the IC that is regulated to about 9 V to 10 V and requires at least 4.7 µF of capacitance to GND; VDD is rated to 12 V absolute maximum. |+| 15 | PGND | power_in | Power ground that serves as a separate ground for the MOSFET drivers and should be connected to the system power ground plane. |+| 16 | LDRV | output | Output driver for the low-side MOSFET, rated to 10 V recommended and 12 V absolute maximum to GND. |+| 17 | BST | power_in | Bootstrap supply for the high-side driver, which must be held above the input voltage, with a minimum 0.1 µF high-frequency capacitor connected from this pin to SW; BST is rated to 12 V absolute maximum to SW. |+| 18 | SW | passive | Switch node connected to the source of the upper MOSFET and the drain of the lower MOSFET and serving as the return path for the high-side gate driver; SW ranges from -3 V to VIN+0.3 V to GND. |+| 19 | HDRV | output | Output driver for the high-side MOSFET, rated to 10 V recommended and 12 V absolute maximum to SW. |+| 20 | VIN | power_in | Input voltage: operates from 12 V to 100 V (absolute maximum 100 V to GND). |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | XDS |+| Package | ETSSOP-20 |+| Category | Power Management (PMIC) |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `TX41601`+- Footprint: `Package_SO:ETSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3x4.2mm`+- 3D model: ETSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `tx41601-etched.step` / `tx41601-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tx41601.step` / `tx41601.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [XDS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234906153684992) (17 pp, sha256 `c126170f7ad9a94e`, retrieved 2026-10-09, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tx41601-datasheet.pdf)
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