component
TX4121
Public Made by Adomby adom
XDS DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+44@@ -0,0 +1,44 @@+# TX4121++**XDS** · DC-DC Converters · ESOP-8++TX4121 from XDS, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | BST | passive | Bootstrap driver pin for the high-side MOSFET gate drive. Connect a 0.1 µF (or larger) ceramic capacitor between BST and SW to develop the high-side gate drive rail. |+| 2 | VDD | power_in | Chip power / converter input supply. Operating range 6.5V to 36V, absolute max 36V. Bypass locally to GND with low-ESR ceramic input capacitors. |+| 3 | SW | power_out | Switching node output - drain junction of the internal high-side and low-side power MOSFETs. Connect to the external inductor. Delivers up to 3.1 A continuous. |+| 4 | GND | power_in | Device ground / power return. Tie to the ground plane together with the EP thermal pad for best thermal and electrical performance. |+| 5 | FB | input | Feedback sense input for the output voltage divider. Regulated to VFB = 0.9 V typical; output OVP threshold VFB_OVP = 0.99 V. Absolute max −0.3 V to 6 V. |+| 6 | COMP | output | Error amplifier output / loop compensation node. Connect an R-C (and optional second C) network from COMP to GND to shape the control-loop response. Source ~5.2 µA, sink ~3.2 µA. |+| 7 | EN | input | Enable input, active-high, with an internal high-value pull-up (~1.6 µA input current). VIH ≥ 1.2 V, VIL ≤ 1.1 V. Absolute max −0.3 V to 6 V. Leave floating or tie high to enable; pull to GND to shut down. |+| 8 | SST | input | Programmable soft-start input. Connect a capacitor from SST to GND; the pin is charged by an internal ~2.3 µA source, ramping the internal reference to control output-voltage rise time and inrush current. Absolute max −0.3 V to 6 V. |+| 9 | EP | passive | Exposed thermal pad on the bottom of the ESOP-8 package. Solder to a large copper ground pour for heat sinking; electrically tie to GND (pin 4). θJA ≈ 56 °C/W, θJC ≈ 45 °C/W. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | XDS |+| Package | ESOP-8 |+| Category | PMIC |+| Pins | 9 |++## CAD (KiCad official)++- Symbol: `TX4121`+- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`+- 3D model: ESOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [XDS datasheet](docs/tx4121-datasheet.pdf) (12 pp, sha256 `d852293a9e759d95`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tx4121-datasheet.pdf)
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