TX4121

@@ -26,13 +26,15 @@       "model_3d_step": "tx4121.step",       "lbr": "tx4121.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C329268"+    },     "pins": [       {         "number": "1",         "name": "BST",         "type": "passive",-        "description": "Bootstrap driver pin for the high-side MOSFET gate drive. Connect a 0.1 µF (or larger) ceramic capacitor between BST and SW to develop the high-side gate drive rail."+        "description": "Bootstrap driver pin for the high-side MOSFET gate drive. Connect a 0.1 \u00b5F (or larger) ceramic capacitor between BST and SW to develop the high-side gate drive rail."       },       {         "number": "2",@@ -56,31 +58,31 @@         "number": "5",         "name": "FB",         "type": "input",-        "description": "Feedback sense input for the output voltage divider. Regulated to VFB = 0.9 V typical; output OVP threshold VFB_OVP = 0.99 V. Absolute max −0.3 V to 6 V."+        "description": "Feedback sense input for the output voltage divider. Regulated to VFB = 0.9 V typical; output OVP threshold VFB_OVP = 0.99 V. Absolute max \u22120.3 V to 6 V."       },       {         "number": "6",         "name": "COMP",         "type": "output",-        "description": "Error amplifier output / loop compensation node. Connect an R-C (and optional second C) network from COMP to GND to shape the control-loop response. Source ~5.2 µA, sink ~3.2 µA."+        "description": "Error amplifier output / loop compensation node. Connect an R-C (and optional second C) network from COMP to GND to shape the control-loop response. Source ~5.2 \u00b5A, sink ~3.2 \u00b5A."       },       {         "number": "7",         "name": "EN",         "type": "input",-        "description": "Enable input, active-high, with an internal high-value pull-up (~1.6 µA input current). VIH ≥ 1.2 V, VIL ≤ 1.1 V. Absolute max −0.3 V to 6 V. Leave floating or tie high to enable; pull to GND to shut down."+        "description": "Enable input, active-high, with an internal high-value pull-up (~1.6 \u00b5A input current). VIH \u2265 1.2 V, VIL \u2264 1.1 V. Absolute max \u22120.3 V to 6 V. Leave floating or tie high to enable; pull to GND to shut down."       },       {         "number": "8",         "name": "SST",         "type": "input",-        "description": "Programmable soft-start input. Connect a capacitor from SST to GND; the pin is charged by an internal ~2.3 µA source, ramping the internal reference to control output-voltage rise time and inrush current. Absolute max −0.3 V to 6 V."+        "description": "Programmable soft-start input. Connect a capacitor from SST to GND; the pin is charged by an internal ~2.3 \u00b5A source, ramping the internal reference to control output-voltage rise time and inrush current. Absolute max \u22120.3 V to 6 V."       },       {         "number": "9",         "name": "EP",         "type": "passive",-        "description": "Exposed thermal pad on the bottom of the ESOP-8 package. Solder to a large copper ground pour for heat sinking; electrically tie to GND (pin 4). θJA ≈ 56 °C/W, θJC ≈ 45 °C/W."+        "description": "Exposed thermal pad on the bottom of the ESOP-8 package. Solder to a large copper ground pour for heat sinking; electrically tie to GND (pin 4). \u03b8JA \u2248 56 \u00b0C/W, \u03b8JC \u2248 45 \u00b0C/W."       }     ],     "provenance": {

@@ -63,6 +63,18 @@   <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="9" x="0.0000" y="-0.0000" dx="2.4100" dy="3.3000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-2.6000" y="2.4700"/>+    <vertex x="-2.8400" y="2.8000"/>+    <vertex x="-2.3600" y="2.8000"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.9750" y="2.4500"/>+    <vertex x="1.9500" y="2.4500"/>+    <vertex x="1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="1.4750"/>+  </polygon>   <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -71,7 +83,7 @@   <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/>   <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="TX4121">@@ -111,7 +123,13 @@         <connect gate="G$1" pin="EN" pad="7"/>         <connect gate="G$1" pin="COMP" pad="6"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="TX4121" constant="no"/>+          <attribute name="MANUFACTURER" value="XDS" constant="no"/>+          <attribute name="LCSC_PN" value="C329268" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>