component
TX4121
Public Made by Adomby adom
XDS DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.md+14@@ -33,6 +33,20 @@ TX4121 from XDS, in a ESOP-8. Pinout and pin descriptions extracted from the man - Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm` - 3D model: ESOP-8 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`tx4121.step`](tx4121.step) | 193 KB | You want the bare part, or you mark your own boards. |+| [`tx4121-etched.step`](tx4121-etched.step) | 834 KB | You want the part with `TX4121` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 236 faces against 63 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "tx4121",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "XDS DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+12−9@@ -4,7 +4,7 @@ "slug": "tx4121", "title": "TX4121", "brief": "XDS DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -34,7 +34,7 @@ "number": "1", "name": "BST", "type": "passive",- "description": "Bootstrap driver pin for the high-side MOSFET gate drive. Connect a 0.1 \u00b5F (or larger) ceramic capacitor between BST and SW to develop the high-side gate drive rail."+ "description": "Bootstrap driver pin for the high-side MOSFET gate drive. Connect a 0.1 µF (or larger) ceramic capacitor between BST and SW to develop the high-side gate drive rail." }, { "number": "2",@@ -58,31 +58,31 @@ "number": "5", "name": "FB", "type": "input",- "description": "Feedback sense input for the output voltage divider. Regulated to VFB = 0.9 V typical; output OVP threshold VFB_OVP = 0.99 V. Absolute max \u22120.3 V to 6 V."+ "description": "Feedback sense input for the output voltage divider. Regulated to VFB = 0.9 V typical; output OVP threshold VFB_OVP = 0.99 V. Absolute max −0.3 V to 6 V." }, { "number": "6", "name": "COMP", "type": "output",- "description": "Error amplifier output / loop compensation node. Connect an R-C (and optional second C) network from COMP to GND to shape the control-loop response. Source ~5.2 \u00b5A, sink ~3.2 \u00b5A."+ "description": "Error amplifier output / loop compensation node. Connect an R-C (and optional second C) network from COMP to GND to shape the control-loop response. Source ~5.2 µA, sink ~3.2 µA." }, { "number": "7", "name": "EN", "type": "input",- "description": "Enable input, active-high, with an internal high-value pull-up (~1.6 \u00b5A input current). VIH \u2265 1.2 V, VIL \u2264 1.1 V. Absolute max \u22120.3 V to 6 V. Leave floating or tie high to enable; pull to GND to shut down."+ "description": "Enable input, active-high, with an internal high-value pull-up (~1.6 µA input current). VIH ≥ 1.2 V, VIL ≤ 1.1 V. Absolute max −0.3 V to 6 V. Leave floating or tie high to enable; pull to GND to shut down." }, { "number": "8", "name": "SST", "type": "input",- "description": "Programmable soft-start input. Connect a capacitor from SST to GND; the pin is charged by an internal ~2.3 \u00b5A source, ramping the internal reference to control output-voltage rise time and inrush current. Absolute max \u22120.3 V to 6 V."+ "description": "Programmable soft-start input. Connect a capacitor from SST to GND; the pin is charged by an internal ~2.3 µA source, ramping the internal reference to control output-voltage rise time and inrush current. Absolute max −0.3 V to 6 V." }, { "number": "9", "name": "EP", "type": "passive",- "description": "Exposed thermal pad on the bottom of the ESOP-8 package. Solder to a large copper ground pour for heat sinking; electrically tie to GND (pin 4). \u03b8JA \u2248 56 \u00b0C/W, \u03b8JC \u2248 45 \u00b0C/W."+ "description": "Exposed thermal pad on the bottom of the ESOP-8 package. Solder to a large copper ground pour for heat sinking; electrically tie to GND (pin 4). θJA ≈ 56 °C/W, θJC ≈ 45 °C/W." } ], "provenance": {@@ -156,6 +156,9 @@ "docs/hero.png", "docs/tx4121-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"- ]+ "viewers/footprint.html",+ "pads.json"+ ],+ "description": "XDS DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "visibility": "public" }