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tx4121: factory component page (tier=lcsc)

Ray ·05dce0fc08 · ·parent e5bb131
1 file changed +122−8
page.json+122−8
@@ -1,13 +1,132 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "tx4121",+  "title": "TX4121",+  "brief": "XDS DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "XDS DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "pmic",     "tx4121"   ],+  "component": {+    "mpn": "TX4121",+    "manufacturer": "XDS",+    "package": "ESOP-8",+    "pin_count": 9,+    "category": "PMIC",+    "subcategory": "DC-DC Converters",+    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/58ebfdc9f832bc68cc8e4c8730fcd71b.pdf",+    "parts": {+      "symbol": "tx4121.kicad_sym",+      "footprint": "tx4121.kicad_mod",+      "model_3d": "tx4121.glb",+      "model_3d_step": "tx4121.step",+      "lbr": "tx4121.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "BST",+        "type": "passive",+        "description": "Bootstrap driver pin for the high-side MOSFET gate drive. Connect a 0.1 \u00b5F (or larger) ceramic capacitor between BST and SW to develop the high-side gate drive rail."+      },+      {+        "number": "2",+        "name": "VDD",+        "type": "power_in",+        "description": "Chip power / converter input supply. Operating range 6.5V to 36V, absolute max 36V. Bypass locally to GND with low-ESR ceramic input capacitors."+      },+      {+        "number": "3",+        "name": "SW",+        "type": "power_out",+        "description": "Switching node output - drain junction of the internal high-side and low-side power MOSFETs. Connect to the external inductor. Delivers up to 3.1 A continuous."+      },+      {+        "number": "4",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground / power return. Tie to the ground plane together with the EP thermal pad for best thermal and electrical performance."+      },+      {+        "number": "5",+        "name": "FB",+        "type": "input",+        "description": "Feedback sense input for the output voltage divider. Regulated to VFB = 0.9 V typical; output OVP threshold VFB_OVP = 0.99 V. Absolute max \u22120.3 V to 6 V."+      },+      {+        "number": "6",+        "name": "COMP",+        "type": "output",+        "description": "Error amplifier output / loop compensation node. Connect an R-C (and optional second C) network from COMP to GND to shape the control-loop response. Source ~5.2 \u00b5A, sink ~3.2 \u00b5A."+      },+      {+        "number": "7",+        "name": "EN",+        "type": "input",+        "description": "Enable input, active-high, with an internal high-value pull-up (~1.6 \u00b5A input current). VIH \u2265 1.2 V, VIL \u2264 1.1 V. Absolute max \u22120.3 V to 6 V. Leave floating or tie high to enable; pull to GND to shut down."+      },+      {+        "number": "8",+        "name": "SST",+        "type": "input",+        "description": "Programmable soft-start input. Connect a capacitor from SST to GND; the pin is charged by an internal ~2.3 \u00b5A source, ramping the internal reference to control output-voltage rise time and inrush current. Absolute max \u22120.3 V to 6 V."+      },+      {+        "number": "9",+        "name": "EP",+        "type": "passive",+        "description": "Exposed thermal pad on the bottom of the ESOP-8 package. Solder to a large copper ground pour for heat sinking; electrically tie to GND (pin 4). \u03b8JA \u2248 56 \u00b0C/W, \u03b8JC \u2248 45 \u00b0C/W."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://datasheet.lcsc.com/datasheet/pdf/58ebfdc9f832bc68cc8e4c8730fcd71b.pdf",+        "pages": 12,+        "sha256": "d852293a9e759d95",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 9,+        "described": 9,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "XDS",+      "Package": "ESOP-8",+      "Category": "PMIC",+      "Pins": "9"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "tx4121"+  ],+  "discovery_pitch": "TX4121 (XDS) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +144,5 @@     "docs/tx4121-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file