TX4115

@@ -0,0 +1,43 @@+# TX4115++**XDS** · DC-DC Converters · SOP-8++TX4115 from XDS, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | FB | input | Output voltage feedback input. Connect to the midpoint of an external resistor divider from VOUT to GND. The internal error amplifier regulates this pin to the 1.21V reference (VREF). R1 = R2*(VOUT/VREF - 1). |+| 2 | TOFF | input | Oscillator/switching frequency setting pin. Connect a resistor from TOFF to GND to set the switching frequency: RTOFF(kΩ) = (6500/Fosc[kHz])^2. Resistor range 130kΩ to 1.5MΩ; leaving TOFF floating defaults to ~130kHz. Internally held at 0.6V. |+| 3 | ILIM | input | Peak current limit programming pin. Connect an external resistor R4 from ILIM to GND to set the peak inductor current limit: R4(kΩ) = 23 * IMAX(A). Typical detection current 8.5µA. If left floating, default peak current limit is 2.7A. |+| 4 | VDD | power_in | Chip supply input, 8V to 30V (absolute max 35V). Bypass with a 100µF low-ESR capacitor to GND close to the pin to suppress input transients. UVLO threshold ~4.25-4.5V. |+| 5 | SW | output | Switching node. Connect the external output inductor here. Internally tied to the drains of both the high-side PMOS and low-side NMOS power switches. Pins 5 and 6 are shorted internally to share switch current. |+| 6 | SW | output | Switching node (parallel with pin 5). Connect the external output inductor here. Tie pins 5 and 6 together for full current handling. |+| 7 | GND | power_in | Chip ground. Analog/power return. Pins 7 and 8 are both GND and should both be tied to the ground plane; they also provide the primary thermal path for the SOP-8 package. |+| 8 | GND | power_in | Chip ground (parallel with pin 7). Tie to the ground plane along with pin 7 for low-impedance return and heat sinking. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | XDS |+| Package | SOP-8 |+| Category | PMIC |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `TX4115`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [XDS datasheet](docs/tx4115-datasheet.pdf) (9 pp, sha256 `5eba4f131236225b`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tx4115-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "tx4115",+  "version": "0.1.0",+  "type": "component",+  "description": "XDS DC-DC Converters, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "pmic",+    "tx4115"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "tx4115.kicad_sym",+    "tx4115.kicad_mod",+    "tx4115.glb",+    "tx4115.step",+    "tx4115.lbr",+    "docs/hero.png",+    "docs/tx4115-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file