component
TSOP57338TT1
Public Made by Adomby adom
Vishay Intertech Infrared Remote Receiver (IRM), DFN-8(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Publish 0.1.0
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README.md+80docs/hero.pngdocs/tsop57338tt1-datasheet.pdfpackage.json+202page.json+208tsop57338tt1-etched.glbtsop57338tt1-hero.glbtsop57338tt1-hero.overlay.json+273tsop57338tt1.glbtsop57338tt1.kicad_mod+259tsop57338tt1.kicad_sym+49tsop57338tt1.lbr+128tsop57338tt1.step+2502viewers/footprint.html+1viewers/symbol.html+1README.mdadded+80@@ -0,0 +1,80 @@+# TSOP57338TT1++**Vishay Intertech** · Infrared Remote Receiver (IRM) · DFN-8(4x4)++TSOP57338TT1 from Vishay Intertech, in a DFN-8(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OUT | output | Demodulated signal output; the absolute maximum output voltage is -0.3 V to (VS + 0.3) V and the output current is limited to 5 mA. |+| 2 | GND | power_in | Ground pin; the package drawing notes that the pins are connected internally and need not be connected externally. |+| 3 | GND | power_in | Ground pin; the package drawing notes that the pins are connected internally and need not be connected externally. |+| 4 | VS | power_in | Supply voltage input; the operating range is 2.0 V to 5.5 V and the absolute maximum rating is -0.3 V to +6 V. |+| 5 | VS | power_in | Supply voltage input; the operating range is 2.0 V to 5.5 V and the absolute maximum rating is -0.3 V to +6 V. |+| 6 | GND | power_in | Ground pin; the package drawing notes that the pins are connected internally and need not be connected externally. |+| 7 | GND | power_in | Ground pin; the package drawing notes that the pins are connected internally and need not be connected externally. |+| 8 | GND | power_in | Ground pin; the package drawing notes that the pins are connected internally and need not be connected externally. |+| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Vishay Intertech |+| Package | DFN-8(4x4) |+| Category | Optoelectronics |+| Pins | 9 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Supply voltage | VS | 2 | | 5.5 | V | | 3 |+| Supply current | ISD | 0.25 | 0.35 | 0.45 | mA | VS = 3.3 V, Ev = 0 | 3 |+| Output voltage low | VOSL | | | 100 | mV | IOSL = 0.5 mA, Ee = 0.7 mW/m2, test signal see Fig. 1 | 3 |+| Minimum irradiance (RC5 code) | Ee min. | | 0.2 | 0.4 | mW/m2 | Test signal: RC5 code | 3 |+| Minimum irradiance (XMP code) | Ee min. | | 0.35 | 0.6 | mW/m2 | Test signal: XMP code | 3 |+| Maximum irradiance | Ee max. | 30 | | | W/m2 | Pulse width tolerance: tpi - 3/fo < tpo < tpi + 3.5/fo, test signal see Fig. 1 | 3 |+| Directivity, angle of half transmission distance | ϕ1/2 | -75 | | 75 | deg | | 3 |+| Supply voltage | VS | -0.3 | | 6 | V | | 2 |+| Supply current | IS | | | 5 | mA | | 2 |+| Output voltage | VO | -0.3 | | | V | | 2 |+| Output current | IO | | | 5 | mA | | 2 |+| Junction temperature | Tj | | | 100 | °C | | 2 |+| Storage temperature range | Tstg | -25 | | 85 | °C | | 2 |+| Operating temperature range | Tamb | -25 | | 85 | °C | | 2 |+| Power consumption | Ptot | | | 10 | mW | Tamb ≤ 85 °C | 2 |+| Minimum burst length | | 6 | | | cycles/burst | TSOP573.. (AGC3) column | 6 |+| Minimum gap after burst of 6 to 40 cycles | | 7 | | | cycles | TSOP573.. (AGC3) column, after each burst of length 6 to 40 cycles | 6 |+| Maximum number of continuous short bursts per second | | | | 2500 | bursts/s | TSOP573.. (AGC3) column | 6 |+| Supply current (high ambient light) | ISH | | 0.45 | | mA | Ev = 40 klx, sunlight | 3 |+| Transmission distance | | | 18 | | m | Ev = 0, IR diode TSAL6200, IF = 50 mA, test signal see Fig. 1 | 3 |++## Materials and finish++As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).++| Part | Material | Colour / plating | Datasheet says | Page |+|---|---|---|---|---|+| housing | PC | | Note: Level and body temperature defined by IPC/JEDEC J-STD-020 | 11 |++## CAD (KiCad official)++- Symbol: `TSOP57338TT1`+- Footprint: `Package_DFN_QFN:DFN-8-1EP_4x4mm_P0.8mm_EP2.5x3.6mm`+- 3D model: DFN-8(4x4) (KiCad packages3D, STEP)+- 3D model files: `tsop57338tt1-etched.step` / `tsop57338tt1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tsop57338tt1.step` / `tsop57338tt1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590406061065863168) (12 pp, sha256 `f516d261f4e06dd2`, retrieved 2026-10-19, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tsop57338tt1-datasheet.pdf)
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package.jsonadded+202@@ -0,0 +1,202 @@+{+ "slug": "tsop57338tt1",+ "version": "0.1.0",+ "type": "component",+ "description": "Vishay Intertech Infrared Remote Receiver (IRM), DFN-8(4x4). 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The only package described is an 8-pin; The pin 1 to pin 8 labels in the page 7 package drawing text are garbled. The drawing text lists 'Ou; The drawing note says pins are connected internally and need not be connected externally, but the no",+ "exposed pad 9 added from the footprint"+ ],+ "pages_sent": 12,+ "cost_usd": 0.0624,+ "at": "2026-10-19T00:06:09"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590406061065863168",+ "pages": 12,+ "sha256": "f516d261f4e06dd2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 9,+ "described": 9,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tsop57338tt1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4.0,+ 3.98,+ 0.92+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "4672964215aa4510e5189d958d9ad3e5259af86a4b80262051b78f0663c358ef",+ "checked": "2026-10-19",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tsop57338tt1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4.0,+ 3.98,+ 0.92+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "1dba4f959462802fa8f82d404a70b36f3ae40e73ec36a218ac8b8f95a505962b",+ "checked": "2026-10-19",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ }+}
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The only package described is an 8-pin; The pin 1 to pin 8 labels in the page 7 package drawing text are garbled. The drawing text lists 'Ou; The drawing note says pins are connected internally and need not be connected externally, but the no",+ "exposed pad 9 added from the footprint"+ ],+ "pages_sent": 12,+ "cost_usd": 0.0624,+ "at": "2026-10-19T00:06:09"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590406061065863168",+ "pages": 12,+ "sha256": "f516d261f4e06dd2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 9,+ "described": 9,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tsop57338tt1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 3.98,+ 0.92+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4672964215aa4510e5189d958d9ad3e5259af86a4b80262051b78f0663c358ef",+ "checked": "2026-10-19",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tsop57338tt1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 3.98,+ 0.92+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "1dba4f959462802fa8f82d404a70b36f3ae40e73ec36a218ac8b8f95a505962b",+ "checked": "2026-10-19",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
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4x4x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)</description>+ <smd name="1" x="-2.0000" y="1.2000" dx="0.7500" dy="0.3500" layer="1"/>+ <smd name="2" x="-2.0000" y="0.4000" dx="0.7500" dy="0.3500" layer="1"/>+ <smd name="3" x="-2.0000" y="-0.4000" dx="0.7500" dy="0.3500" layer="1"/>+ <smd name="4" x="-2.0000" y="-1.2000" dx="0.7500" dy="0.3500" layer="1"/>+ <smd name="5" x="2.0000" y="-1.2000" dx="0.7500" dy="0.3500" layer="1"/>+ <smd name="6" x="2.0000" y="-0.4000" dx="0.7500" dy="0.3500" layer="1"/>+ <smd name="7" x="2.0000" y="0.4000" dx="0.7500" dy="0.3500" layer="1"/>+ <smd name="8" x="2.0000" y="1.2000" dx="0.7500" dy="0.3500" layer="1"/>+ <smd name="9" x="0.0000" y="-0.0000" dx="2.5000" dy="3.6000" layer="1" cream="no"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-2.5600" y="1.5600"/>+ <vertex x="-3.0400" y="1.5600"/>+ <vertex x="-2.5600" y="2.0400"/>+ <vertex x="-2.5600" y="1.5600"/>+ </polygon>+ <wire x1="-2.0000" y1="2.1100" x2="2.0000" y2="2.1100" width="0.1200" layer="21"/>+ <wire x1="-2.0000" y1="-2.1100" x2="2.0000" y2="-2.1100" width="0.1200" layer="21"/>+ <wire x1="-2.0000" y1="1.0000" x2="-1.0000" y2="2.0000" width="0.1000" layer="51"/>+ <wire x1="-2.0000" y1="-2.0000" x2="-2.0000" y2="1.0000" width="0.1000" layer="51"/>+ <wire x1="-1.0000" y1="2.0000" x2="2.0000" y2="2.0000" width="0.1000" layer="51"/>+ <wire x1="2.0000" y1="2.0000" x2="2.0000" y2="-2.0000" width="0.1000" layer="51"/>+ <wire x1="2.0000" y1="-2.0000" x2="-2.0000" y2="-2.0000" width="0.1000" layer="51"/>+ <text x="0" y="2.710" size="1.27" layer="25" align="bottom-center">>NAME</text>+ <text x="0" y="-2.710" size="1.27" layer="27" align="top-center">>VALUE</text>+</package>+</packages>+<symbols>+<symbol name="TSOP57338TT1">+ <wire x1="-12.7" y1="7.62" x2="12.7" y2="7.62" width="0.254" layer="94"/>+ <wire x1="12.7" y1="7.62" x2="12.7" y2="-7.62" width="0.254" layer="94"/>+ <wire x1="12.7" y1="-7.62" x2="-12.7" y2="-7.62" width="0.254" layer="94"/>+ <wire x1="-12.7" y1="-7.62" x2="-12.7" y2="7.62" width="0.254" layer="94"/>+ <text x="0.0000" y="10.1600" size="1.27" layer="95" align="center">>NAME</text>+ <text x="0.0000" y="-10.1600" size="1.27" layer="96" align="center">>VALUE</text>+ <pin name="OUT" x="-17.78" y="5.08" length="middle" direction="out"/>+ <pin name="GND" x="-17.78" y="2.54" length="middle" direction="pwr"/>+ <pin name="GND@2" x="-17.78" y="0" length="middle" direction="pwr"/>+ <pin name="VS" x="-17.78" y="-2.54" length="middle" direction="pwr"/>+ <pin name="VS@2" x="-17.78" y="-5.08" length="middle" direction="pwr"/>+ <pin name="EP" x="17.78" y="2.54" length="middle" direction="pas" rot="R180"/>+ <pin name="GND@3" x="17.78" y="0" length="middle" direction="pwr" rot="R180"/>+ <pin name="GND@4" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="GND@5" x="17.78" y="-5.08" length="middle" direction="pwr" rot="R180"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="TSOP57338TT1" prefix="U">+ <description></description>+ <gates>+ <gate name="G$1" symbol="TSOP57338TT1" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="DFN-8-1EP_4x4mm_P0.8mm_EP2.5x3.6mm">+ <connects>+ <connect gate="G$1" pin="OUT" pad="1"/>+ <connect gate="G$1" pin="GND" pad="2"/>+ <connect gate="G$1" pin="GND@2" pad="3"/>+ <connect gate="G$1" pin="VS" pad="4"/>+ <connect gate="G$1" pin="VS@2" pad="5"/>+ <connect gate="G$1" pin="EP" pad="9"/>+ <connect gate="G$1" pin="GND@3" pad="8"/>+ <connect gate="G$1" pin="GND@4" pad="7"/>+ <connect gate="G$1" pin="GND@5" pad="6"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
tsop57338tt1.stepadded+2502@@ -0,0 +1,2502 @@+ISO-10303-21; +HEADER; +/* DFN-8-1EP_4x4mm_Pitch0.8mm.step 3D STEP model for use in ECAD systems + * Copyright (C) 2017, kicad StepUp + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + * + * As a special exception, if you create a design which uses this symbol, + * and embed this symbol or unaltered portions of this symbol into the design, + * this symbol does not by itself cause the resulting design to be covered by + * the GNU General Public License. + * This exception does not however invalidate any other reasons why the design + * itself might be covered by the GNU General Public License. + * If you modify this symbol, you may extend this exception to your version of the symbol, + * but you are not obligated to do so. + * If you do not wish to do so, delete this exception statement from your version + * Risk disclaimer + * *USE 3D CAD DATA AT YOUR OWN RISK* + * *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.* + * + */ + +FILE_DESCRIPTION( +/* description */ ('model of DFN-8-1EP_4x4mm_Pitch0.8mm'), +/* implementation_level */ '2;1'); + +FILE_NAME( +/* name */ 'DFN-8-1EP_4x4mm_Pitch0.8mm.step', +/* time_stamp */ '2017-03-23T11:15:53', +/* author */ ('kicad StepUp','ksu'), +/* organization */ ('FreeCAD'), +/* preprocessor_version */ 'OCC', +/* originating_system */ 'kicad StepUp', +/* authorisation */ ''); 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viewers/footprint.htmladded+1@@ -0,0 +1 @@+<!doctype html><title>tsop57338tt1</title>
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