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TPS7A4701
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TI ultra-low-noise, high-PSRR LDO, VQFN-20. 36 V in, 1 A, pin-programmable output, 4 uVrms noise. Datasheet-verified.
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README.mdadded+64@@ -0,0 +1,64 @@+# TPS7A4701++**Texas Instruments** · LDO regulator · VQFN-20++Low-noise linear regulator for supplying sensitive analog: data converters, PLLs, and RF, where switching ripple would corrupt the signal. It takes up to 36 V, delivers 1 A, and outputs about 4 uVrms of noise with high power-supply rejection across frequency, so it scrubs a noisy upstream rail. The output is set in fine steps by grounding binary-weighted programming pins (0.1 V through 6.4 V taps) rather than an external divider. A cleanup regulator for the quiet rails on a mixed-signal board.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OUT | power_out | Regulator output. Tie a ≥10 µF (47 µF ceramic recommended) capacitor from OUT to GND close to the device for stability and best AC performance. Pin 1 and pin 20 are internally connected and must be tied together. |+| 2 | NC | unconnected | No internal connection. May be left open or tied to any voltage between GND and IN. |+| 3 | SENSE/FB | input | Control-loop error amplifier input (TPS7A4701 only). Acts as SENSE when using ANY-OUT programming (tie to OUT at point of load) or as FB when using an external resistor divider for adjustable operation up to 34V. |+| 4 | 6P4V2 | input | ANY-OUT output-voltage programming pin. Tie to GND to add 6.4 V to the nominal output voltage. Leave floating if unused. Do not connect to any voltage other than GND. |+| 5 | 6P4V1 | input | ANY-OUT output-voltage programming pin. Tie to GND to add 6.4 V to the nominal output voltage. Leave floating if unused. Do not connect to any voltage other than GND. |+| 6 | 3P2V | input | ANY-OUT output-voltage programming pin. Tie to GND to add 3.2 V to the nominal output voltage. Leave floating if unused. Do not connect to any voltage other than GND. |+| 7 | GND | power_in | Device ground. Internally connected to the thermal pad. |+| 8 | 1P6V | input | ANY-OUT output-voltage programming pin. Tie to GND to add 1.6 V to the nominal output voltage. Leave floating if unused. Do not connect to any voltage other than GND. |+| 9 | 0P8V | input | ANY-OUT output-voltage programming pin. Tie to GND to add 0.8 V to the nominal output voltage. Leave floating if unused. Do not connect to any voltage other than GND. |+| 10 | 0P4V | input | ANY-OUT output-voltage programming pin. Tie to GND to add 0.4 V to the nominal output voltage. Leave floating if unused. Do not connect to any voltage other than GND. |+| 11 | 0P2V | input | ANY-OUT output-voltage programming pin. Tie to GND to add 0.2 V to the nominal output voltage. Leave floating if unused. Do not connect to any voltage other than GND. |+| 12 | 0P1V | input | ANY-OUT output-voltage programming pin. Tie to GND to add 0.1 V to the nominal output voltage. Leave floating if unused. Do not connect to any voltage other than GND. |+| 13 | EN | input | Enable. Device is enabled when VEN exceeds VEN(HI). Absolute max 36 V to GND. Tie to IN if enable control is not required. |+| 14 | NR | passive | Noise reduction pin. Connect a ≥10 nF capacitor from NR to GND (1 µF recommended, placed close to the device) to reduce output RMS noise to the 4 µVRMS spec and stabilize the reference. |+| 15 | IN | power_in | Input supply (+3 V to +36 V). Tie a ≥1 µF capacitor from IN to GND for stability; 10 µF is recommended, placed close to the device. Pins 15 and 16 are internally connected. |+| 16 | IN | power_in | Input supply (+3 V to +36 V). Tie a ≥1 µF capacitor from IN to GND for stability; 10 µF is recommended. Pins 15 and 16 are internally connected. |+| 17 | NC | unconnected | No internal connection. May be left open or tied to any voltage between GND and IN. |+| 18 | NC | unconnected | No internal connection. May be left open or tied to any voltage between GND and IN. |+| 19 | NC | unconnected | No internal connection. May be left open or tied to any voltage between GND and IN. |+| 20 | OUT | power_out | Regulator output. Tie a ≥10 µF (47 µF ceramic recommended) capacitor from OUT to GND close to the device. Pin 1 and pin 20 are internally connected and must be tied together. |+| 21 | GND | power_in | Thermal pad. Internally connected to GND. Solder to a large-area ground plane for proper thermal performance and electrical grounding. |++## Key specifications++| Parameter | Value |+|---|---|+| Type | Ultra-low-noise LDO |+| Input | 3-36 V |+| Output | 1.4-20.5 V (pin-programmable) |+| Output current | 1 A |+| Noise | 4.17 uVrms (10 Hz-100 kHz) |+| PSRR | High across frequency |+| Package | VQFN-20 |++## Ordering variants++- `TPS7A4701RGWR (VQFN-20)`+- `TPS7A4700RGWR (fixed-adjust variant)`++## CAD (KiCad official)++- Symbol: `Regulator_Linear2:TPS7A4701xRGW (KiCad official)`+- Footprint: `Package_DFN_QFN:Texas_RGW0020A_VQFN-20-1EP_5x5mm_P0.65mm_EP3.15x3.15mm_ThermalVias`+- 3D model: VQFN-20 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps7a47.pdf) (32 pp, sha256 `8ca46a9968923d2e`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps7a47-datasheet.pdf)
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