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TPS70748PWP
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+57@@ -0,0 +1,57 @@+# TPS70748PWP++**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20-EP++TPS70748PWP from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | No connection; the pin is not connected internally and may be left open. |+| 2 | VIN1 | power_in | Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps regulator 1 off until VIN1 reaches 2.5 V. |+| 3 | VIN1 | power_in | Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps regulator 1 off until VIN1 reaches 2.5 V. |+| 4 | MR1 | input | Manual reset input 1, active low, with an internal 6-µA pull-up to VIN1; a logic low triggers a POR (RESET). |+| 5 | MR2 | input | Manual reset input 2, active low, with an internal 6-µA pull-up to VIN1; a logic low triggers a POR (RESET). |+| 6 | EN | input | Active-low enable: the device is enabled when EN is at a low level and is put into sleep mode (about 1 µA input current at TJ = +25°C) when EN is driven high. |+| 7 | SEQ | input | Power-up sequence control: high or open turns VOUT2 on first, low turns VOUT1 on first; the pin has an internal 6-µA pull-up to VIN1. |+| 8 | GND | power_in | Ground reference for the device. |+| 9 | VIN2 | power_in | Input voltage of regulator 2. |+| 10 | VIN2 | power_in | Input voltage of regulator 2. |+| 11 | NC | unconnected | No connection; the pin is not connected internally and may be left open. |+| 12 | VOUT2 | power_out | Output voltage of regulator 2, rated for up to 125 mA. |+| 13 | VOUT2 | power_out | Output voltage of regulator 2, rated for up to 125 mA. |+| 14 | VSENSE2/FB2 | input | Regulator 2 output voltage sense on fixed versions (connect to VOUT2 as close as possible) or feedback input on the adjustable version, to be tied to the external resistor divider. |+| 15 | RESET | output | Open-drain, active-low power-on reset output that goes low when VOUT2 is below 95% of its regulated voltage or a manual reset input is low, and needs a pull-up resistor. |+| 16 | PG1 | output | Open-drain power-good output that is low when VOUT1 is below 95% of its regulated voltage and needs a pull-up resistor. |+| 17 | VSENSE1/FB1 | input | Regulator 1 output voltage sense on fixed versions (connect to VOUT1 as close as possible) or feedback input on the adjustable version, to be tied to the external resistor divider. |+| 18 | VOUT1 | power_out | Output voltage of regulator 1, rated for up to 250 mA. |+| 19 | VOUT1 | power_out | Output voltage of regulator 1, rated for up to 250 mA. |+| 20 | NC | unconnected | No connection; the pin is not connected internally and may be left open. |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-20-EP |+| Category | Power Management (PMIC) |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `TPS70748PWP`+- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`+- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `tps70748pwp-etched.step` / `tps70748pwp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps70748pwp.step` / `tps70748pwp.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps707) (45 pp, sha256 `47c201c539729fd2`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps70748pwp-datasheet.pdf)
page.jsonadded+279@@ -0,0 +1,279 @@+{+ "slug": "tps70748pwp",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps70748pwp",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps70748pwp.kicad_sym",+ "tps70748pwp.kicad_mod",+ "tps70748pwp.glb",+ "tps70748pwp.step",+ "tps70748pwp.lbr",+ "docs/hero.png",+ "docs/tps70748pwp-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps70748pwp-hero.glb",+ "tps70748pwp-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS70748PWP",+ "manufacturer": "Texas Instruments",+ "package": "HTSSOP-20-EP",+ "pin_count": 21,+ "category": "Power Management (PMIC)",+ "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps707",+ "parts": {+ "symbol": "tps70748pwp.kicad_sym",+ "footprint": "tps70748pwp.kicad_mod",+ "model_3d": "tps70748pwp-hero.glb",+ "model_3d_plain": "tps70748pwp.glb",+ "model_3d_step": "tps70748pwp-etched.step",+ "model_3d_step_plain": "tps70748pwp.step",+ "lbr": "tps70748pwp.lbr"+ },+ "distributor_links": {+ "lcsc": "C2870792",+ "digikey": "2156-TPS70748PWP-ND",+ "mouser": "595-TPS70748PWP"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:55:06Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-TPS70748PWP-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS70748PWP",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; the pin is not connected internally and may be left open."+ },+ {+ "number": "2",+ "name": "VIN1",+ "type": "power_in",+ "description": "Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps regulator 1 off until VIN1 reaches 2.5 V."+ },+ {+ "number": "3",+ "name": "VIN1",+ "type": "power_in",+ "description": "Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps regulator 1 off until VIN1 reaches 2.5 V."+ },+ {+ "number": "4",+ "name": "MR1",+ "type": "input",+ "description": "Manual reset input 1, active low, with an internal 6-µA pull-up to VIN1; a logic low triggers a POR (RESET)."+ },+ {+ "number": "5",+ "name": "MR2",+ "type": "input",+ "description": "Manual reset input 2, active low, with an internal 6-µA pull-up to VIN1; a logic low triggers a POR (RESET)."+ },+ {+ "number": "6",+ "name": "EN",+ "type": "input",+ "description": "Active-low enable: the device is enabled when EN is at a low level and is put into sleep mode (about 1 µA input current at TJ = +25°C) when EN is driven high."+ },+ {+ "number": "7",+ "name": "SEQ",+ "type": "input",+ "description": "Power-up sequence control: high or open turns VOUT2 on first, low turns VOUT1 on first; the pin has an internal 6-µA pull-up to VIN1."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "9",+ "name": "VIN2",+ "type": "power_in",+ "description": "Input voltage of regulator 2."+ },+ {+ "number": "10",+ "name": "VIN2",+ "type": "power_in",+ "description": "Input voltage of regulator 2."+ },+ {+ "number": "11",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; the pin is not connected internally and may be left open."+ },+ {+ "number": "12",+ "name": "VOUT2",+ "type": "power_out",+ "description": "Output voltage of regulator 2, rated for up to 125 mA."+ },+ {+ "number": "13",+ "name": "VOUT2",+ "type": "power_out",+ "description": "Output voltage of regulator 2, rated for up to 125 mA."+ },+ {+ "number": "14",+ "name": "VSENSE2/FB2",+ "type": "input",+ "description": "Regulator 2 output voltage sense on fixed versions (connect to VOUT2 as close as possible) or feedback input on the adjustable version, to be tied to the external resistor divider."+ },+ {+ "number": "15",+ "name": "RESET",+ "type": "output",+ "description": "Open-drain, active-low power-on reset output that goes low when VOUT2 is below 95% of its regulated voltage or a manual reset input is low, and needs a pull-up resistor."+ },+ {+ "number": "16",+ "name": "PG1",+ "type": "output",+ "description": "Open-drain power-good output that is low when VOUT1 is below 95% of its regulated voltage and needs a pull-up resistor."+ },+ {+ "number": "17",+ "name": "VSENSE1/FB1",+ "type": "input",+ "description": "Regulator 1 output voltage sense on fixed versions (connect to VOUT1 as close as possible) or feedback input on the adjustable version, to be tied to the external resistor divider."+ },+ {+ "number": "18",+ "name": "VOUT1",+ "type": "power_out",+ "description": "Output voltage of regulator 1, rated for up to 250 mA."+ },+ {+ "number": "19",+ "name": "VOUT1",+ "type": "power_out",+ "description": "Output voltage of regulator 1, rated for up to 250 mA."+ },+ {+ "number": "20",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; the pin is not connected internally and may be left open."+ },+ {+ "number": "21",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package count conflict in the datasheet: the ordering table (page 3) labels the TPS70748PWP as HTSSO; The PowerPAD exposed thermal pad is not given a pin number in the supplied pages, and its connection; The pin-to-number mapping was reconstructed from the garbled top-view text on page 1 and cross-check",+ "exposed pad 21 added from the footprint"+ ],+ "pages_sent": 11,+ "cost_usd": 0.0808,+ "at": "2026-10-08T16:54:43"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps707",+ "pages": 45,+ "sha256": "47c201c539729fd2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps70748pwp.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7b48ea25b01e9633c23bbd5739f911dccc743209cafe4a606006531e3dff5813",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps70748pwp-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f7b4d20aa6078777416c092800d4e7de268cc9619a3a9a5a52f1f2471f7725a1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}