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TPS6521825RSLR
Public Made by Adomby adom
Texas Instruments Power Management - Specialized, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# TPS6521825RSLR++**Texas Instruments** · Power Management - Specialized · VQFN-48-EP(6x6)++TPS6521825RSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN_DCDC1 | power_in | Input supply pin for DCDC1. |+| 2 | SDA | bidirectional | Data line for the I2C interface; connect to a pullup resistor. |+| 3 | SCL | input | Clock input for the I2C interface; connect to a pullup resistor. |+| 4 | LDO1 | power_out | Output voltage pin for LDO1; connect to a capacitor. |+| 5 | IN_LDO1 | power_in | Input supply pin for LDO1. |+| 6 | IN_LS3 | power_in | Input supply pin for load switch 3. |+| 7 | LS3 | power_out | Output voltage pin for load switch 3; connect to a capacitor. |+| 8 | PGOOD | output | Power-good output, open drain; pulled low when DCDC1-4 or LDO1 are out of regulation, and load switches and DCDC5-6 do not affect it. |+| 9 | AC_DET | input | AC monitor input and enable for DCDC1-4, LDO1 and load switches; tie to IN_BIAS if not used. |+| 10 | nPFO | output | Deglitched power-fail comparator output, open drain; pulled low when the PFI input is below the power-fail threshold. |+| 11 | GPIO1 | bidirectional | Configurable as DDR reset input (driving GPO2) or as a general-purpose open-drain output. |+| 12 | IN_DCDC4 | power_in | Input supply pin for DCDC4. |+| 13 | L4A | power_out | Switch pin for DCDC4; connect to inductor. |+| 14 | L4B | power_out | Switch pin for DCDC4; connect to inductor. |+| 15 | DCDC4 | power_out | Output voltage pin for DCDC4; connect to a capacitor. |+| 16 | PFI | input | Power-fail comparator input; connect to a resistor divider. |+| 17 | DC34_SEL | input | Power-up default selection pin for DCDC3 or DCDC4, programmed by a resistor to ground (resistor options in section 8.3.1.13). |+| 18 | IN_nCC | output | Push-pull output indicating whether DCDC5 and DCDC6 are powered from IN_BU (high) or the coin cell CC (low). |+| 19 | PGOOD_BU | output | Push-pull power-good output for DCDC5 and DCDC6; low when either is out of regulation, and high (at DCDC6 output voltage) when both are in regulation. |+| 20 | L5 | power_out | Switch pin for DCDC5; connect to inductor. |+| 21 | FB5 | input | Feedback voltage pin for DCDC5; connect to output capacitor. |+| 22 | FB6 | input | Feedback voltage pin for DCDC6; connect to output capacitor. |+| 23 | L6 | power_out | Switch pin for DCDC6; connect to inductor. |+| 24 | SYS_BU | power_out | System voltage pin for the battery-backup supply path; connect to a 1-µF capacitor, and connecting any external load is not recommended. |+| 25 | CC | power_in | Coin-cell battery input that supplies DCDC5 and DCDC6 when no voltage is applied to IN_BU; tie to ground if not in use. |+| 26 | GPIO3 | bidirectional | Configurable as warm reset (negative edge) for DCDC1 and DCDC2, or as a general-purpose open-drain output. |+| 27 | IN_BU | power_in | Default input supply pin for the battery-backup supplies (DCDC5 and DCDC6). |+| 28 | N/C | unconnected | No connect; leave pin floating. |+| 29 | N/C | unconnected | No connect; leave pin floating. |+| 30 | LS1 | power_out | Output voltage pin for load switch 1; connect to a capacitor. |+| 31 | IN_LS1 | power_in | Input supply pin for load switch 1. |+| 32 | IN_LS2 | power_in | Input supply pin for load switch 2. |+| 33 | LS2 | power_out | Output voltage pin for load switch 2; connect to a capacitor. |+| 34 | GPO2 | output | DDR reset signal controlled by GPIO1, or a general-purpose output; buffer configurable as push-pull or open drain, with 6 mA source/sink limit. |+| 35 | INT_LDO | power_out | Internal bias voltage; connect to a 1-µF capacitor, and TI does not recommend connecting any external load. |+| 36 | IN_BIAS | power_in | Input supply pin for the reference system. |+| 37 | IN_DCDC3 | power_in | Input supply pin for DCDC3. |+| 38 | L3 | power_out | Switch pin for DCDC3; connect to inductor. |+| 39 | FB3 | input | Feedback voltage pin for DCDC3; connect to output capacitor. |+| 40 | nWAKEUP | output | Signal to the SoC indicating a power-on event (active low, open-drain output). |+| 41 | FB2 | input | Feedback voltage pin for DCDC2; connect to output capacitor. |+| 42 | L2 | power_out | Switch pin for DCDC2; connect to inductor. |+| 43 | IN_DCDC2 | power_in | Input supply pin for DCDC2. |+| 44 | PB | input | Push-button monitor input, typically a momentary switch to ground (active low). |+| 45 | nINT | output | Interrupt output (active low, open drain); pulled low when an interrupt bit is set and released after the bit is read. |+| 46 | PWR_EN | input | Power-enable input for DCDC1-4, LDO1 and load switches. |+| 47 | FB1 | input | Feedback voltage pin for DCDC1; connect to output capacitor. |+| 48 | L1 | power_out | Switch pin for DCDC1; connect to inductor. |+| 49 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(6x6) |+| Category | Power Management (PMIC) |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `TPS6521825RSLR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm`+- 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `tps6521825rslr-etched.step` / `tps6521825rslr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps6521825rslr.step` / `tps6521825rslr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps6521825) (94 pp, sha256 `d04b48faa7750415`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps6521825rslr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps6521825rslr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps6521825rslr.kicad_sym",+ "tps6521825rslr.kicad_mod",+ "tps6521825rslr.glb",+ "tps6521825rslr.step",+ "tps6521825rslr.lbr",+ "docs/hero.png",+ "docs/tps6521825rslr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps6521825rslr-hero.glb",+ "tps6521825rslr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS6521825RSLR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(6x6)",+ "pin_count": 49,+ "category": "Power Management (PMIC)",+ "subcategory": "Power Management - Specialized",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps6521825",+ "parts": {+ "symbol": "tps6521825rslr.kicad_sym",+ "footprint": "tps6521825rslr.kicad_mod",+ "model_3d": "tps6521825rslr-hero.glb",+ "model_3d_plain": "tps6521825rslr.glb",+ "model_3d_step": "tps6521825rslr-etched.step",+ "model_3d_step_plain": "tps6521825rslr.step",+ "lbr": "tps6521825rslr.lbr"+ },+ "distributor_links": {+ "lcsc": "C1852159",+ "digikey": "296-TPS6521825RSLRTR-ND",+ "mouser": "595-TPS6521825RSLR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:51:18Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-TPS6521825RSLRTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS6521825RSLR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "IN_DCDC1",+ "type": "power_in",+ "description": "Input supply pin for DCDC1."+ },+ {+ "number": "2",+ "name": "SDA",+ "type": "bidirectional",+ "description": "Data line for the I2C interface; connect to a pullup resistor."+ },+ {+ "number": "3",+ "name": "SCL",+ "type": "input",+ "description": "Clock input for the I2C interface; connect to a pullup resistor."+ },+ {+ "number": "4",+ "name": "LDO1",+ "type": "power_out",+ "description": "Output voltage pin for LDO1; connect to a capacitor."+ },+ {+ "number": "5",+ "name": "IN_LDO1",+ "type": "power_in",+ "description": "Input supply pin for LDO1."+ },+ {+ "number": "6",+ "name": "IN_LS3",+ "type": "power_in",+ "description": "Input supply pin for load switch 3."+ },+ {+ "number": "7",+ "name": "LS3",+ "type": "power_out",+ "description": "Output voltage pin for load switch 3; connect to a capacitor."+ },+ {+ "number": "8",+ "name": "PGOOD",+ "type": "output",+ "description": "Power-good output, open drain; pulled low when DCDC1-4 or LDO1 are out of regulation, and load switches and DCDC5-6 do not affect it."+ },+ {+ "number": "9",+ "name": "AC_DET",+ "type": "input",+ "description": "AC monitor input and enable for DCDC1-4, LDO1 and load switches; tie to IN_BIAS if not used."+ },+ {+ "number": "10",+ "name": "nPFO",+ "type": "output",+ "description": "Deglitched power-fail comparator output, open drain; pulled low when the PFI input is below the power-fail threshold."+ },+ {+ "number": "11",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "Configurable as DDR reset input (driving GPO2) or as a general-purpose open-drain output."+ },+ {+ "number": "12",+ "name": "IN_DCDC4",+ "type": "power_in",+ "description": "Input supply pin for DCDC4."+ },+ {+ "number": "13",+ "name": "L4A",+ "type": "power_out",+ "description": "Switch pin for DCDC4; connect to inductor."+ },+ {+ "number": "14",+ "name": "L4B",+ "type": "power_out",+ "description": "Switch pin for DCDC4; connect to inductor."+ },+ {+ "number": "15",+ "name": "DCDC4",+ "type": "power_out",+ "description": "Output voltage pin for DCDC4; connect to a capacitor."+ },+ {+ "number": "16",+ "name": "PFI",+ "type": "input",+ "description": "Power-fail comparator input; connect to a resistor divider."+ },+ {+ "number": "17",+ "name": "DC34_SEL",+ "type": "input",+ "description": "Power-up default selection pin for DCDC3 or DCDC4, programmed by a resistor to ground (resistor options in section 8.3.1.13)."+ },+ {+ "number": "18",+ "name": "IN_nCC",+ "type": "output",+ "description": "Push-pull output indicating whether DCDC5 and DCDC6 are powered from IN_BU (high) or the coin cell CC (low)."+ },+ {+ "number": "19",+ "name": "PGOOD_BU",+ "type": "output",+ "description": "Push-pull power-good output for DCDC5 and DCDC6; low when either is out of regulation, and high (at DCDC6 output voltage) when both are in regulation."+ },+ {+ "number": "20",+ "name": "L5",+ "type": "power_out",+ "description": "Switch pin for DCDC5; connect to inductor."+ },+ {+ "number": "21",+ "name": "FB5",+ "type": "input",+ "description": "Feedback voltage pin for DCDC5; connect to output capacitor."+ },+ {+ "number": "22",+ "name": "FB6",+ "type": "input",+ "description": "Feedback voltage pin for DCDC6; connect to output capacitor."+ },+ {+ "number": "23",+ "name": "L6",+ "type": "power_out",+ "description": "Switch pin for DCDC6; connect to inductor."+ },+ {+ "number": "24",+ "name": "SYS_BU",+ "type": "power_out",+ "description": "System voltage pin for the battery-backup supply path; connect to a 1-µF capacitor, and connecting any external load is not recommended."+ },+ {+ "number": "25",+ "name": "CC",+ "type": "power_in",+ "description": "Coin-cell battery input that supplies DCDC5 and DCDC6 when no voltage is applied to IN_BU; tie to ground if not in use."+ },+ {+ "number": "26",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "Configurable as warm reset (negative edge) for DCDC1 and DCDC2, or as a general-purpose open-drain output."+ },+ {+ "number": "27",+ "name": "IN_BU",+ "type": "power_in",+ "description": "Default input supply pin for the battery-backup supplies (DCDC5 and DCDC6)."+ },+ {+ "number": "28",+ "name": "N/C",+ "type": "unconnected",+ "description": "No connect; leave pin floating."+ },+ {+ "number": "29",+ "name": "N/C",+ "type": "unconnected",+ "description": "No connect; leave pin floating."+ },+ {+ "number": "30",+ "name": "LS1",+ "type": "power_out",+ "description": "Output voltage pin for load switch 1; connect to a capacitor."+ },+ {+ "number": "31",+ "name": "IN_LS1",+ "type": "power_in",+ "description": "Input supply pin for load switch 1."+ },+ {+ "number": "32",+ "name": "IN_LS2",+ "type": "power_in",+ "description": "Input supply pin for load switch 2."+ },+ {+ "number": "33",+ "name": "LS2",+ "type": "power_out",+ "description": "Output voltage pin for load switch 2; connect to a capacitor."+ },+ {+ "number": "34",+ "name": "GPO2",+ "type": "output",+ "description": "DDR reset signal controlled by GPIO1, or a general-purpose output; buffer configurable as push-pull or open drain, with 6 mA source/sink limit."+ },+ {+ "number": "35",+ "name": "INT_LDO",+ "type": "power_out",+ "description": "Internal bias voltage; connect to a 1-µF capacitor, and TI does not recommend connecting any external load."+ },+ {+ "number": "36",+ "name": "IN_BIAS",+ "type": "power_in",+ "description": "Input supply pin for the reference system."+ },+ {+ "number": "37",+ "name": "IN_DCDC3",+ "type": "power_in",+ "description": "Input supply pin for DCDC3."+ },+ {+ "number": "38",+ "name": "L3",+ "type": "power_out",+ "description": "Switch pin for DCDC3; connect to inductor."+ },+ {+ "number": "39",+ "name": "FB3",+ "type": "input",+ "description": "Feedback voltage pin for DCDC3; connect to output capacitor."+ },+ {+ "number": "40",+ "name": "nWAKEUP",+ "type": "output",+ "description": "Signal to the SoC indicating a power-on event (active low, open-drain output)."+ },+ {+ "number": "41",+ "name": "FB2",+ "type": "input",+ "description": "Feedback voltage pin for DCDC2; connect to output capacitor."+ },+ {+ "number": "42",+ "name": "L2",+ "type": "power_out",+ "description": "Switch pin for DCDC2; connect to inductor."+ },+ {+ "number": "43",+ "name": "IN_DCDC2",+ "type": "power_in",+ "description": "Input supply pin for DCDC2."+ },+ {+ "number": "44",+ "name": "PB",+ "type": "input",+ "description": "Push-button monitor input, typically a momentary switch to ground (active low)."+ },+ {+ "number": "45",+ "name": "nINT",+ "type": "output",+ "description": "Interrupt output (active low, open drain); pulled low when an interrupt bit is set and released after the bit is read."+ },+ {+ "number": "46",+ "name": "PWR_EN",+ "type": "input",+ "description": "Power-enable input for DCDC1-4, LDO1 and load switches."+ },+ {+ "number": "47",+ "name": "FB1",+ "type": "input",+ "description": "Feedback voltage pin for DCDC1; connect to output capacitor."+ },+ {+ "number": "48",+ "name": "L1",+ "type": "power_out",+ "description": "Switch pin for DCDC1; connect to inductor."+ },+ {+ "number": "49",+ "name": "Thermal Pad",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed thermal pad (Table 6-1 row '— Thermal Pad', power ground and thermal relief, connect to ; The datasheet classes these as P (power) or O (output) without KiCad types. I mapped switch nodes an; Pins 28 and 29 are marked N/C in the datasheet, so they are typed unconnected.",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 13,+ "cost_usd": 0.0961,+ "at": "2026-10-08T20:50:20"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps6521825",+ "pages": 94,+ "sha256": "d04b48faa7750415",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps6521825rslr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.9+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f5021c40cb4e3beba7b3a41b40bc2f2020d2f1ec96a4ac7d5ff47ccf196390a0",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps6521825rslr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.02,+ 6.02,+ 0.9+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d0a238d3f717ae9a1c2de868a0ffc9e3d6668a47e03a1bb33bda0d8083c00e76",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}