component
TPS65131RGER
Public Made by Adomby adom
Texas Instruments DC-DC Converters, QFN-24-EP(4x4). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+64@@ -0,0 +1,64 @@+# TPS65131RGER++**Texas Instruments** · DC-DC Converters · QFN-24-EP(4x4)++TPS65131RGER from Texas Instruments, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | INP | input | Boost converter switch input. Connect to the boost inductor node; a second pin (24) is bonded to the same net. Absolute maximum 17 V. |+| 2 | PGND | power_in | Power ground pin for the switching stages. Tie together with pin 3 and the PowerPAD to the board ground plane. |+| 3 | PGND | power_in | Power ground pin for the switching stages. Tie together with pin 2 and the PowerPAD to the board ground plane. |+| 4 | VIN | power_in | Control supply input. 2.7 V to 5.5 V operating range; UVLO threshold ~2.35 V. Provides bias to the internal control circuitry. |+| 5 | INN | input | Inverting converter switch input. Connect to the inverter inductor node; a second pin (6) is bonded to the same net. |+| 6 | INN | input | Inverting converter switch input. Connect to the inverter inductor node; a second pin (5) is bonded to the same net. |+| 7 | BSW | output | Gate control pin for an external battery-disconnect PFET. Pulls low when ENP is set high to turn on the external PFET; output resistance ~27 kΩ. |+| 8 | ENP | input | Enable pin for the positive (boost) output. 0 V = disabled, VIN = enabled. VIH ≥ 1.4 V, VIL ≤ 0.4 V. Used for power-up/down sequencing. |+| 9 | PSP | input | Power-save mode enable for the boost converter stage. 0 V = disabled (forced PWM), VIN = enabled (pulse-skipping at light loads). |+| 10 | ENN | input | Enable pin for the negative (inverter) output. 0 V = disabled, VIN = enabled. VIH ≥ 1.4 V, VIL ≤ 0.4 V. Used for power-up/down sequencing. |+| 11 | PSN | input | Power-save mode enable for the inverter stage. 0 V = disabled (forced PWM), VIN = enabled (pulse-skipping at light loads). |+| 12 | NC | unconnected | No internal connection. Leave floating or tie to ground. |+| 13 | OUTN | output | Inverting converter switch output. Connect to the flying capacitor / rectifying diode of the inverter stage; a second pin (14) is bonded to the same net. |+| 14 | OUTN | output | Inverting converter switch output. Connect to the flying capacitor / rectifying diode of the inverter stage; a second pin (13) is bonded to the same net. |+| 15 | VNEG | input | Negative output voltage sense input. Ties to the regulated negative output rail (adjustable down to -15 V) for internal reference of the inverter output. |+| 16 | FBN | input | Feedback pin for the negative output voltage divider. Regulated to 0 V (±24 mV) with respect to VREF at the divider tap. |+| 17 | VREF | output | Reference output voltage, typ. 1.213 V. Bypass with a 220-nF capacitor to ground. Connect the lower resistor of the negative output voltage divider to this pin. |+| 18 | CN | passive | Compensation pin for the inverting converter control loop. Connect the loop-compensation R-C network from this pin to GND/AGND. |+| 19 | AGND | power_in | Analog ground pin. Reference for the internal control circuitry; tie to the ground plane close to the PowerPAD. |+| 20 | NC | unconnected | No internal connection. Leave floating or tie to ground. |+| 21 | CP | passive | Compensation pin for the boost converter control loop. Connect the loop-compensation R-C network from this pin to GND/AGND. |+| 22 | FBP | input | Feedback pin for the positive output voltage divider. Regulated to 1.213 V (typ.). |+| 23 | VPOS | input | Positive output voltage sense input. Ties to the regulated positive output rail (adjustable VIN+0.5 V up to 15 V). |+| 24 | INP | input | Boost converter switch input. Connect to the boost inductor node; a second pin (1) is bonded to the same net. Absolute maximum 17 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | QFN-24-EP(4x4) |+| Category | PMIC |+| Pins | 24 |++## Ordering variants++- `TPS65131RGER`+- `TPS65131RGERRGET`++## CAD (KiCad official)++- Symbol: `TPS65131RGER`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`+- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps65131rger.pdf) (32 pp, sha256 `2d70b7f1a656b110`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps65131rger-datasheet.pdf)
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