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TPS650942A0RSKR
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Texas Instruments Power Management - Specialized, VQFN-64-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+102@@ -0,0 +1,102 @@+# TPS650942A0RSKR++**Texas Instruments** · Power Management - Specialized · VQFN-64-EP(8x8)++TPS650942A0RSKR from Texas Instruments, in a VQFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | FBGND2 | power_in | Remote negative feedback sense for the BUCK2 controller; connect to the VCCGI VSS sense from the SoC. |+| 2 | FBVOUT2 | input | Remote positive feedback sense for the BUCK2 controller; connect to the VCCGI VCC sense from the SoC. |+| 3 | DRVH2 | output | High-side gate driver output for the BUCK2 controller, operating at VSYS + 5 V. |+| 4 | SW2 | input | Switch node connection for the BUCK2 controller. |+| 5 | BOOT2 | input | Bootstrap pin for the BUCK2 controller at VSYS + 5 V; connect a 100-nF ceramic capacitor between this pin and SW2. |+| 6 | PGNDSNS2 | power_in | Power ground connection for BUCK2; connect to the ground terminal of the external low-side FET. |+| 7 | DRVL2 | output | Low-side gate driver output for the BUCK2 controller at 5 V. |+| 8 | DRV5V_2_A1 | power_in | 5-V supply to the BUCK2 gate driver and LDOA1; bypass to ground with a 2.2-µF (typical) ceramic capacitor, shorted on board to LDO5P0. |+| 9 | LDOA1 | power_out | LDOA1 output at 1.35 to 3.3 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use. |+| 10 | LX3 | output | Switch node connection for the BUCK3 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR. |+| 11 | PVIN3 | power_in | 5-V power input to the BUCK3 converter; bypass to ground with a 10-µF (typical) ceramic capacitor. |+| 12 | FB3 | input | Remote feedback sense for the BUCK3 converter; connect to the positive terminal of the output capacitor. |+| 13 | PMICEN | input | PMIC cold-boot pin; its rising edge moves the power state from G3 to S4/S5, and driving it low shuts down all VRs. |+| 14 | LDOLS_EN or SWA1_EN | input | Enable pin for LDOA2, LDOA3 and SWA1 when OTP is LDOLS_EN, or for SWA1 only when OTP is SWA1_EN; resources turn on at high and off at low. |+| 15 | IRQB | output | Open-drain output interrupt pin; see the IRQ register definitions in the datasheet. |+| 16 | RSMRSTB | output | Open-drain always-on-rail power good that reflects a valid state whenever VSYS is available. |+| 17 | SWB1 | power_out | Output of load switch B1 at 0.5 to 3.3 V (1.8 V typical); bypass with a 0.1-µF (typical) ceramic capacitor and short with SWB2. |+| 18 | PVINSWB1_B2 | power_in | Power supply to load switches B1 and B2 at 0.5 to 3.3 V; bypass with a 1-µF (typical) ceramic capacitor and connect to ground when not in use. |+| 19 | SWB2 | power_out | Output of load switch B2 at 0.5 to 3.3 V (1.8 V typical); bypass with a 0.1-µF (typical) ceramic capacitor, short with SWB1, and leave floating when not in use. |+| 20 | LX5 | output | Switch node connection for the BUCK5 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR. |+| 21 | PVIN5 | power_in | 5-V power input to the BUCK5 converter; bypass to ground with a 10-µF (typical) ceramic capacitor. |+| 22 | FB5 | input | Remote feedback sense for the BUCK5 converter; connect to the positive terminal of the output capacitor. |+| 23 | FB4 | input | Remote feedback sense for the BUCK4 converter; connect to the positive terminal of the output capacitor. |+| 24 | PVIN4 | power_in | 5-V power input to the BUCK4 converter; bypass to ground with a 10-µF (typical) ceramic capacitor. |+| 25 | LX4 | output | Switch node connection for the BUCK4 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR. |+| 26 | GPO | output | Open-drain output controlled by the GPO_CTRL register bit, usable as an enable signal for an external VR. |+| 27 | PCH_PWROK | output | Open-drain global power good that reflects a valid state whenever VSYS is available. |+| 28 | PROCHOT | output | Optional open-drain output indicating a PMIC thermal event when any die sensor detects THOT; invert before connecting to the SoC if used, otherwise leave floating. |+| 29 | FBVOUT1 | input | Remote feedback sense for the BUCK1 controller; connect to the VNN VCC sense from the SoC. |+| 30 | ILIM1 | input | Current-limit set pin for the BUCK1 controller; fit a resistor from this pin to ground to set the external low-side FET current limit. |+| 31 | SWA1 | power_out | Output of load switch A1 at 0.5 to 3.3 V; bypass with a 0.1-µF (typical) ceramic capacitor and leave floating when not in use. |+| 32 | PVINSWA1 | power_in | Power supply to load switch A1 at 0.5 to 3.3 V; bypass with a 1-µF (typical) ceramic capacitor and connect to ground when not in use. |+| 33 | DRVH1 | output | High-side gate driver output for the BUCK1 controller, operating at VSYS + 5 V. |+| 34 | SW1 | input | Switch node connection for the BUCK1 controller. |+| 35 | BOOT1 | input | Bootstrap pin for the BUCK1 controller at VSYS + 5 V; connect a 100-nF ceramic capacitor between this pin and SW1. |+| 36 | PGNDSNS1 | power_in | Power ground connection for BUCK1; connect to the ground terminal of the external low-side FET. |+| 37 | DRVL1 | output | Low-side gate driver output for the BUCK1 controller at 5 V. |+| 38 | DRV5V_1_6 | power_in | 5-V supply to the BUCK1 and BUCK6 gate drivers; bypass to ground with a 2.2-µF (typical) ceramic capacitor, shorted on board to LDO5P0. |+| 39 | DRVL6 | output | Low-side gate driver output for the BUCK6 controller at 5 V. |+| 40 | PGNDSNS6 | power_in | Power ground connection for BUCK6; connect to the ground terminal of the external low-side FET. |+| 41 | BOOT6 | input | Bootstrap pin for the BUCK6 controller at VSYS + 5 V; connect a 100-nF ceramic capacitor between this pin and SW6. |+| 42 | SW6 | input | Switch node connection for the BUCK6 controller. |+| 43 | DRVH6 | output | High-side gate driver output for the BUCK6 controller, operating at VSYS + 5 V. |+| 44 | FBVOUT6 | input | Remote feedback sense for the BUCK6 controller; connect to the positive terminal of the output capacitor. |+| 45 | ILIM6 | input | Current-limit set pin for the BUCK6 controller; fit a resistor from this pin to ground to set the external low-side FET current limit. |+| 46 | PVINVTT | power_in | Power supply to the VTT LDO from VDDQ; bypass to ground with a 10-µF (minimum) ceramic capacitor and connect to ground when not in use. |+| 47 | VTT | power_out | Output of the VTT LDO at VDDQ/2; bypass to ground with 2 x 22-µF (minimum) ceramic capacitors and leave floating when not in use. |+| 48 | VTTFB | input | Remote feedback sense for the VTT LDO at VDDQ/2; connect to the positive terminal of the output capacitor and short to GND when not in use. |+| 49 | LDOA3 | power_out | Output of LDOA3 at 0.7 to 1.5 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use. |+| 50 | PVINLDOA2_A3 | power_in | 1.8-V power supply to LDOA2 and LDOA3; bypass to ground with a 4.7-µF (typical) ceramic capacitor and connect to ground when not in use. |+| 51 | LDOA2 | power_out | Output of LDOA2 at 0.7 to 1.5 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use. |+| 52 | AGND | power_in | Analog ground that must not be connected to the top-layer thermal pad ground; connect it to the ground of the VREF capacitor. |+| 53 | VREF | power_out | Band-gap reference output at 1.25 V; stabilize with a 100-nF (typical) ceramic capacitor to quiet ground. |+| 54 | LDO3P3 | power_out | Output of the 3.3-V internal LDO; bypass to ground with a 4.7-µF (typical) ceramic capacitor. |+| 55 | VSYS | power_in | System voltage detection and input to the internal 3.3-V and 5-V LDOs; bypass to ground with a 1-µF (typical) ceramic capacitor. |+| 56 | LDO5P0 | power_out | Output of the 5-V internal LDO or of an internal switch connecting to V5ANA; bypass to ground with a 4.7-µF (typical) ceramic capacitor. |+| 57 | V5ANA | power_in | External 5-V supply input to the internal load switch that connects to LDO5P0; an optional ceramic bypass improves transient performance. |+| 58 | CLK | input | I2C clock input. |+| 59 | DATA | bidirectional | I2C data line. |+| 60 | THERMTRIPB | input | Thermal shutdown signal from the SoC. |+| 61 | SLP_S0B | input | Power-state pin; the PMIC enters Connected Standby on the falling edge and exits on the rising edge. |+| 62 | SLP_S3B | input | Power-state pin; the PMIC enters S3 on the falling edge and exits to S0 on the rising edge. |+| 63 | SLP_S4B | input | Power-state pin; the PMIC enters S4 on the falling edge and exits to S3 on the rising edge. |+| 64 | ILIM2 | input | Current-limit set pin for the BUCK2 controller; fit a resistor from this pin to ground to set the external low-side FET current limit. |+| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-64-EP(8x8) |+| Category | Power Management (PMIC) |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `TPS650942A0RSKR`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm`+- 3D model: VQFN-64-EP(8x8) (KiCad packages3D, STEP)+- 3D model files: `tps650942a0rskr-etched.step` / `tps650942a0rskr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps650942a0rskr.step` / `tps650942a0rskr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps65094) (94 pp, sha256 `5f0839e7e2610575`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps650942a0rskr-datasheet.pdf)
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connect to the VCCGI VSS sense from the SoC."+ },+ {+ "number": "2",+ "name": "FBVOUT2",+ "type": "input",+ "description": "Remote positive feedback sense for the BUCK2 controller; connect to the VCCGI VCC sense from the SoC."+ },+ {+ "number": "3",+ "name": "DRVH2",+ "type": "output",+ "description": "High-side gate driver output for the BUCK2 controller, operating at VSYS + 5 V."+ },+ {+ "number": "4",+ "name": "SW2",+ "type": "input",+ "description": "Switch node connection for the BUCK2 controller."+ },+ {+ "number": "5",+ "name": "BOOT2",+ "type": "input",+ "description": "Bootstrap pin for the BUCK2 controller at VSYS + 5 V; connect a 100-nF ceramic capacitor between this pin and SW2."+ },+ {+ "number": "6",+ "name": "PGNDSNS2",+ "type": "power_in",+ "description": "Power ground connection for BUCK2; connect to the ground terminal of the external low-side FET."+ },+ {+ "number": "7",+ "name": "DRVL2",+ "type": "output",+ "description": "Low-side gate driver output for the BUCK2 controller at 5 V."+ },+ {+ "number": "8",+ "name": "DRV5V_2_A1",+ "type": "power_in",+ "description": "5-V supply to the BUCK2 gate driver and LDOA1; bypass to ground with a 2.2-µF (typical) ceramic capacitor, shorted on board to LDO5P0."+ },+ {+ "number": "9",+ "name": "LDOA1",+ "type": "power_out",+ "description": "LDOA1 output at 1.35 to 3.3 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use."+ },+ {+ "number": "10",+ "name": "LX3",+ "type": "output",+ "description": "Switch node connection for the BUCK3 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR."+ },+ {+ "number": "11",+ "name": "PVIN3",+ "type": "power_in",+ "description": "5-V power input to the BUCK3 converter; bypass to ground with a 10-µF (typical) ceramic capacitor."+ },+ {+ "number": "12",+ "name": "FB3",+ "type": "input",+ "description": "Remote feedback sense for the BUCK3 converter; connect to the positive terminal of the output capacitor."+ },+ {+ "number": "13",+ "name": "PMICEN",+ "type": "input",+ "description": "PMIC cold-boot pin; its rising edge moves the power state from G3 to S4/S5, and driving it low shuts down all VRs."+ },+ {+ "number": "14",+ "name": "LDOLS_EN or SWA1_EN",+ "type": "input",+ "description": "Enable pin for LDOA2, LDOA3 and SWA1 when OTP is LDOLS_EN, or for SWA1 only when OTP is SWA1_EN; resources turn on at high and off at low."+ },+ {+ "number": "15",+ "name": "IRQB",+ "type": "output",+ "description": "Open-drain output interrupt pin; see the IRQ register definitions in the datasheet."+ },+ {+ "number": "16",+ "name": "RSMRSTB",+ "type": "output",+ "description": "Open-drain always-on-rail power good that reflects a valid state whenever VSYS is available."+ },+ {+ "number": "17",+ "name": "SWB1",+ "type": "power_out",+ "description": "Output of load switch B1 at 0.5 to 3.3 V (1.8 V typical); bypass with a 0.1-µF (typical) ceramic capacitor and short with SWB2."+ },+ {+ "number": "18",+ "name": "PVINSWB1_B2",+ "type": "power_in",+ "description": "Power supply to load switches B1 and B2 at 0.5 to 3.3 V; bypass with a 1-µF (typical) ceramic capacitor and connect to ground when not in use."+ },+ {+ "number": "19",+ "name": "SWB2",+ "type": "power_out",+ "description": "Output of load switch B2 at 0.5 to 3.3 V (1.8 V typical); bypass with a 0.1-µF (typical) ceramic capacitor, short with SWB1, and leave floating when not in use."+ },+ {+ "number": "20",+ "name": "LX5",+ "type": "output",+ "description": "Switch node connection for the BUCK5 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR."+ },+ {+ "number": "21",+ "name": "PVIN5",+ "type": "power_in",+ "description": "5-V power input to the BUCK5 converter; bypass to ground with a 10-µF (typical) ceramic capacitor."+ },+ {+ "number": "22",+ "name": "FB5",+ "type": "input",+ "description": "Remote feedback sense for the BUCK5 converter; connect to the positive terminal of the output capacitor."+ },+ {+ "number": "23",+ "name": "FB4",+ "type": "input",+ "description": "Remote feedback sense for the BUCK4 converter; connect to the positive terminal of the output capacitor."+ },+ {+ "number": "24",+ "name": "PVIN4",+ "type": "power_in",+ "description": "5-V power input to the BUCK4 converter; bypass to ground with a 10-µF (typical) ceramic capacitor."+ },+ {+ "number": "25",+ "name": "LX4",+ "type": "output",+ "description": "Switch node connection for the BUCK4 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR."+ },+ {+ "number": "26",+ "name": "GPO",+ "type": "output",+ "description": "Open-drain output controlled by the GPO_CTRL register bit, usable as an enable signal for an external VR."+ },+ {+ "number": "27",+ "name": "PCH_PWROK",+ "type": "output",+ "description": "Open-drain global power good that reflects a valid state whenever VSYS is available."+ },+ {+ "number": "28",+ "name": "PROCHOT",+ "type": "output",+ "description": "Optional open-drain output indicating a PMIC thermal event when any die sensor detects THOT; invert before connecting to the SoC if used, otherwise leave floating."+ },+ {+ "number": "29",+ "name": "FBVOUT1",+ "type": "input",+ "description": "Remote feedback sense for the BUCK1 controller; connect to the VNN VCC sense from the SoC."+ },+ {+ "number": "30",+ "name": "ILIM1",+ "type": "input",+ "description": "Current-limit set pin for the BUCK1 controller; fit a resistor from this pin to ground to set the external low-side FET current limit."+ },+ {+ "number": "31",+ "name": "SWA1",+ "type": "power_out",+ "description": "Output of load switch A1 at 0.5 to 3.3 V; bypass with a 0.1-µF (typical) ceramic capacitor and leave floating when not in use."+ },+ {+ "number": "32",+ "name": "PVINSWA1",+ "type": "power_in",+ "description": "Power supply to load switch A1 at 0.5 to 3.3 V; bypass with a 1-µF (typical) ceramic capacitor and connect to ground when not in use."+ },+ {+ "number": "33",+ "name": "DRVH1",+ "type": "output",+ "description": "High-side gate driver output for the BUCK1 controller, operating at VSYS + 5 V."+ },+ {+ "number": "34",+ "name": "SW1",+ "type": "input",+ "description": "Switch node connection for the BUCK1 controller."+ },+ {+ "number": "35",+ "name": "BOOT1",+ "type": "input",+ "description": "Bootstrap pin for the BUCK1 controller at VSYS + 5 V; connect a 100-nF ceramic capacitor between this pin and SW1."+ },+ {+ "number": "36",+ "name": "PGNDSNS1",+ "type": "power_in",+ "description": "Power ground connection for BUCK1; connect to the ground terminal of the external low-side FET."+ },+ {+ "number": "37",+ "name": "DRVL1",+ "type": "output",+ "description": "Low-side gate driver output for the BUCK1 controller at 5 V."+ },+ {+ "number": "38",+ "name": "DRV5V_1_6",+ "type": "power_in",+ "description": "5-V supply to the BUCK1 and BUCK6 gate drivers; bypass to ground with a 2.2-µF (typical) ceramic capacitor, shorted on board to LDO5P0."+ },+ {+ "number": "39",+ "name": "DRVL6",+ "type": "output",+ "description": "Low-side gate driver output for the BUCK6 controller at 5 V."+ },+ {+ "number": "40",+ "name": "PGNDSNS6",+ "type": "power_in",+ "description": "Power ground connection for BUCK6; connect to the ground terminal of the external low-side FET."+ },+ {+ "number": "41",+ "name": "BOOT6",+ "type": "input",+ "description": "Bootstrap pin for the BUCK6 controller at VSYS + 5 V; connect a 100-nF ceramic capacitor between this pin and SW6."+ },+ {+ "number": "42",+ "name": "SW6",+ "type": "input",+ "description": "Switch node connection for the BUCK6 controller."+ },+ {+ "number": "43",+ "name": "DRVH6",+ "type": "output",+ "description": "High-side gate driver output for the BUCK6 controller, operating at VSYS + 5 V."+ },+ {+ "number": "44",+ "name": "FBVOUT6",+ "type": "input",+ "description": "Remote feedback sense for the BUCK6 controller; connect to the positive terminal of the output capacitor."+ },+ {+ "number": "45",+ "name": "ILIM6",+ "type": "input",+ "description": "Current-limit set pin for the BUCK6 controller; fit a resistor from this pin to ground to set the external low-side FET current limit."+ },+ {+ "number": "46",+ "name": "PVINVTT",+ "type": "power_in",+ "description": "Power supply to the VTT LDO from VDDQ; bypass to ground with a 10-µF (minimum) ceramic capacitor and connect to ground when not in use."+ },+ {+ "number": "47",+ "name": "VTT",+ "type": "power_out",+ "description": "Output of the VTT LDO at VDDQ/2; bypass to ground with 2 x 22-µF (minimum) ceramic capacitors and leave floating when not in use."+ },+ {+ "number": "48",+ "name": "VTTFB",+ "type": "input",+ "description": "Remote feedback sense for the VTT LDO at VDDQ/2; connect to the positive terminal of the output capacitor and short to GND when not in use."+ },+ {+ "number": "49",+ "name": "LDOA3",+ "type": "power_out",+ "description": "Output of LDOA3 at 0.7 to 1.5 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use."+ },+ {+ "number": "50",+ "name": "PVINLDOA2_A3",+ "type": "power_in",+ "description": "1.8-V power supply to LDOA2 and LDOA3; bypass to ground with a 4.7-µF (typical) ceramic capacitor and connect to ground when not in use."+ },+ {+ "number": "51",+ "name": "LDOA2",+ "type": "power_out",+ "description": "Output of LDOA2 at 0.7 to 1.5 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use."+ },+ {+ "number": "52",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground that must not be connected to the top-layer thermal pad ground; connect it to the ground of the VREF capacitor."+ },+ {+ "number": "53",+ "name": "VREF",+ "type": "power_out",+ "description": "Band-gap reference output at 1.25 V; stabilize with a 100-nF (typical) ceramic capacitor to quiet ground."+ },+ {+ "number": "54",+ "name": "LDO3P3",+ "type": "power_out",+ "description": "Output of the 3.3-V internal LDO; bypass to ground with a 4.7-µF (typical) ceramic capacitor."+ },+ {+ "number": "55",+ "name": "VSYS",+ "type": "power_in",+ "description": "System voltage detection and input to the internal 3.3-V and 5-V LDOs; bypass to ground with a 1-µF (typical) ceramic capacitor."+ },+ {+ "number": "56",+ "name": "LDO5P0",+ "type": "power_out",+ "description": "Output of the 5-V internal LDO or of an internal switch connecting to V5ANA; bypass to ground with a 4.7-µF (typical) ceramic capacitor."+ },+ {+ "number": "57",+ "name": "V5ANA",+ "type": "power_in",+ "description": "External 5-V supply input to the internal load switch that connects to LDO5P0; an optional ceramic bypass improves transient performance."+ },+ {+ "number": "58",+ "name": "CLK",+ "type": "input",+ "description": "I2C clock input."+ },+ {+ "number": "59",+ "name": "DATA",+ "type": "bidirectional",+ "description": "I2C data line."+ },+ {+ "number": "60",+ "name": "THERMTRIPB",+ "type": "input",+ "description": "Thermal shutdown signal from the SoC."+ },+ {+ "number": "61",+ "name": "SLP_S0B",+ "type": "input",+ "description": "Power-state pin; the PMIC enters Connected Standby on the falling edge and exits on the rising edge."+ },+ {+ "number": "62",+ "name": "SLP_S3B",+ "type": "input",+ "description": "Power-state pin; the PMIC enters S3 on the falling edge and exits to S0 on the rising edge."+ },+ {+ "number": "63",+ "name": "SLP_S4B",+ "type": "input",+ "description": "Power-state pin; the PMIC enters S4 on the falling edge and exits to S3 on the rising edge."+ },+ {+ "number": "64",+ "name": "ILIM2",+ "type": "input",+ "description": "Current-limit set pin for the BUCK2 controller; fit a resistor from this pin to ground to set the external low-side FET current limit."+ },+ {+ "number": "65",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Thermal pad (labelled PGND/Thermal Pad on the top view) has no pin number in the datasheet's pin tab; Pin 1 FBGND2 is listed as type I in the datasheet; it is a remote ground sense, so it was classified; Pin 14 has a dual-function name (LDOLS_EN or SWA1_EN) that depends on OTP configuration; the name is",+ "exposed pad 65 added from the footprint"+ ],+ "pages_sent": 18,+ "cost_usd": 0.1617,+ "at": "2026-10-08T18:27:26"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps65094",+ "pages": 94,+ "sha256": "5f0839e7e2610575",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps650942a0rskr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 8,+ 8,+ 0.87+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "553641350988a3d949874ef3cbbe3efa6e239859177963f45ba4e900f4c74ccf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps650942a0rskr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 8,+ 8,+ 0.87+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3bfae5b4b79e161d6c0c1389af67b6297acb481d1b5813d39731b70c0841d72f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}