component
TPS61175QPWPRQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-14-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+10−7@@ -44,13 +44,13 @@ "number": "3", "name": "VIN", "type": "power_in",- "description": "Input supply pin for the IC control circuitry. Accepts 2.9 V to 18 V; may be biased from a source different than the boost power stage input if the application requires operation above the 18 V VIN range. Bypass with a low-ESR ceramic capacitor (\u22654.7 \u03bcF) to PGND close to the pin."+ "description": "Input supply pin for the IC control circuitry. Accepts 2.9 V to 18 V; may be biased from a source different than the boost power stage input if the application requires operation above the 18 V VIN range. Bypass with a low-ESR ceramic capacitor (≥4.7 μF) to PGND close to the pin." }, { "number": "4", "name": "EN", "type": "input",- "description": "Enable input. Logic-high (V_ENIH \u2265 1.2 V) enables the converter; when the pin falls below the enable-low threshold (V_ENIL \u2264 0.4 V) for more than 10 ms, the IC turns off. Contains an internal ~800 k\u03a9 pull-down resistor to GND. Absolute-max rating is 20 V."+ "description": "Enable input. Logic-high (V_ENIH ≥ 1.2 V) enables the converter; when the pin falls below the enable-low threshold (V_ENIL ≤ 0.4 V) for more than 10 ms, the IC turns off. Contains an internal ~800 kΩ pull-down resistor to GND. Absolute-max rating is 20 V." }, { "number": "5",@@ -62,7 +62,7 @@ "number": "6", "name": "SYNC", "type": "input",- "description": "Switching frequency synchronization input. Accepts an external clock (V_SYN \u2264 5 V, high \u2265 1.2 V, low \u2264 0.4 V) between 200 kHz and 2.2 MHz to lock the internal oscillator. If unused, tie directly to AGND with the shortest possible trace to avoid noise coupling."+ "description": "Switching frequency synchronization input. Accepts an external clock (V_SYN ≤ 5 V, high ≥ 1.2 V, low ≤ 0.4 V) between 200 kHz and 2.2 MHz to lock the internal oscillator. If unused, tie directly to AGND with the shortest possible trace to avoid noise coupling." }, { "number": "7",@@ -74,7 +74,7 @@ "number": "8", "name": "COMP", "type": "output",- "description": "Output of the internal transconductance (gm \u2248 340 \u03bcmho) error amplifier. Connect an external RC compensation network from COMP to AGND to shape the control loop response. Internal clamp voltages are 3 V (high) and 0.75 V (low)."+ "description": "Output of the internal transconductance (gm ≈ 340 μmho) error amplifier. Connect an external RC compensation network from COMP to AGND to shape the control loop response. Internal clamp voltages are 3 V (high) and 0.75 V (low)." }, { "number": "9",@@ -86,7 +86,7 @@ "number": "10", "name": "FREQ", "type": "passive",- "description": "Switching frequency programming pin. An external resistor from FREQ to AGND sets the internal oscillator frequency (e.g. 480 k\u03a9 \u2248 210 kHz, 80 k\u03a9 \u2248 1.2 MHz, 40 k\u03a9 \u2248 2.2 MHz). Pin sits at ~1.229 V."+ "description": "Switching frequency programming pin. An external resistor from FREQ to AGND sets the internal oscillator frequency (e.g. 480 kΩ ≈ 210 kHz, 80 kΩ ≈ 1.2 MHz, 40 kΩ ≈ 2.2 MHz). Pin sits at ~1.229 V." }, { "number": "11",@@ -116,7 +116,7 @@ "number": "15", "name": "PAD", "type": "power_in",- "description": "Exposed PowerPAD on the underside of the HTSSOP package. Must be soldered to the analog ground copper for electrical connection and thermal dissipation; use multiple thermal vias to internal and bottom ground planes for optimum \u03b8_JA (45.2 \u00b0C/W)."+ "description": "Exposed PowerPAD on the underside of the HTSSOP package. Must be soldered to the analog ground copper for electrical connection and thermal dissipation; use multiple thermal vias to internal and bottom ground planes for optimum θ_JA (45.2 °C/W)." } ], "provenance": {@@ -186,5 +186,8 @@ "docs/tps61175qpwprq1-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }