TPS61175QPWPRQ1

@@ -0,0 +1,57 @@+# TPS61175QPWPRQ1++**Texas Instruments** · DC-DC Converters · HTSSOP-14-EP++TPS61175QPWPRQ1 from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SW | power_out | Switching node of the internal 40 V / 3 A power MOSFET drain. Pins 1 and 2 are tied together internally and must be connected to the switched side of the inductor / rectifier diode. Route with wide, short traces to minimize EMI and switching losses. |+| 2 | SW | power_out | Switching node of the internal 40 V / 3 A power MOSFET drain. Pins 1 and 2 are tied together internally and must be connected to the switched side of the inductor / rectifier diode. Route with wide, short traces to minimize EMI and switching losses. |+| 3 | VIN | power_in | Input supply pin for the IC control circuitry. Accepts 2.9 V to 18 V; may be biased from a source different than the boost power stage input if the application requires operation above the 18 V VIN range. Bypass with a low-ESR ceramic capacitor (≥4.7 μF) to PGND close to the pin. |+| 4 | EN | input | Enable input. Logic-high (V_ENIH ≥ 1.2 V) enables the converter; when the pin falls below the enable-low threshold (V_ENIL ≤ 0.4 V) for more than 10 ms, the IC turns off. Contains an internal ~800 kΩ pull-down resistor to GND. Absolute-max rating is 20 V. |+| 5 | SS | passive | Soft-start programming pin. A capacitor from SS to GND sets the output voltage ramp-up time and limits inrush current at startup. Refer to the datasheet application section for capacitor sizing (max pin voltage 7 V). |+| 6 | SYNC | input | Switching frequency synchronization input. Accepts an external clock (V_SYN ≤ 5 V, high ≥ 1.2 V, low ≤ 0.4 V) between 200 kHz and 2.2 MHz to lock the internal oscillator. If unused, tie directly to AGND with the shortest possible trace to avoid noise coupling. |+| 7 | AGND | power_in | Analog/signal ground return for the internal control circuitry. Must be tied to the system ground plane; connect the thermal pad to this net at a single quiet ground reference point separated from the high-current PGND path. |+| 8 | COMP | output | Output of the internal transconductance (gm ≈ 340 μmho) error amplifier. Connect an external RC compensation network from COMP to AGND to shape the control loop response. Internal clamp voltages are 3 V (high) and 0.75 V (low). |+| 9 | FB | input | Feedback input for output voltage regulation. Connect the midpoint of an external resistor divider from V_OUT to FB; the internal reference regulates this pin to V_REF = 1.229 V (typ). Input bias current is 200 nA (max). |+| 10 | FREQ | passive | Switching frequency programming pin. An external resistor from FREQ to AGND sets the internal oscillator frequency (e.g. 480 kΩ ≈ 210 kHz, 80 kΩ ≈ 1.2 MHz, 40 kΩ ≈ 2.2 MHz). Pin sits at ~1.229 V. |+| 11 | NC | passive | Reserved pin. The datasheet requires this pin be connected to ground for proper operation; do not leave floating and do not connect to any external signal. |+| 12 | PGND | power_in | Power ground return connected to the source of the internal PWM power MOSFET. Pins 12, 13, and 14 are internally tied and must be connected to a low-impedance ground plane with short, wide traces to handle the switch current. |+| 13 | PGND | power_in | Power ground return connected to the source of the internal PWM power MOSFET. Pins 12, 13, and 14 are internally tied and must be connected to a low-impedance ground plane with short, wide traces to handle the switch current. |+| 14 | PGND | power_in | Power ground return connected to the source of the internal PWM power MOSFET. Pins 12, 13, and 14 are internally tied and must be connected to a low-impedance ground plane with short, wide traces to handle the switch current. |+| 15 | PAD | power_in | Exposed PowerPAD on the underside of the HTSSOP package. Must be soldered to the analog ground copper for electrical connection and thermal dissipation; use multiple thermal vias to internal and bottom ground planes for optimum θ_JA (45.2 °C/W). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-14-EP |+| Category | Power Management (PMIC) |+| Pins | 15 |++## Ordering variants++Same part, different packaging or reel option.++- `TPS61175QPWPRQ1`++## CAD (KiCad official)++- Symbol: `TPS61175QPWPRQ1`+- Footprint: `Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm`+- 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps61175-q1) (30 pp, sha256 `55bee4dd568920d3`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps61175qpwprq1-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "tps61175qpwprq1",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments DC-DC Converters, HTSSOP-14-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "tps61175qpwprq1"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "tps61175qpwprq1.kicad_sym",+    "tps61175qpwprq1.kicad_mod",+    "tps61175qpwprq1.glb",+    "tps61175qpwprq1.step",+    "tps61175qpwprq1.lbr",+    "docs/hero.png",+    "docs/tps61175qpwprq1-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file