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TPS54672PWPR
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Texas Instruments DC-DC Converters, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+65@@ -0,0 +1,65 @@+# TPS54672PWPR++**Texas Instruments** · DC-DC Converters · HTSSOP-28-EP++TPS54672PWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGND | power_in | Analog ground and return for the compensation network/output divider, VBIAS capacitor, and RT resistor; connect the PowerPAD to AGND. |+| 2 | VSENSE | input | Error amplifier inverting input, connected to the output voltage through the compensation network/output divider. |+| 3 | COMP | output | Error amplifier output; the frequency compensation network connects from COMP to VSENSE. |+| 4 | STATUS | output | Open-drain output that is asserted low when VIN is below the UVLO threshold, VBIAS and the internal reference are not settled, or thermal shutdown is active, and is otherwise high; sink current is limited to 10 mA absolute maximum. |+| 5 | BOOT | output | Bootstrap output; a 0.022 µF to 0.1 µF low-ESR capacitor from BOOT to PH generates the floating drive for the high-side FET driver, with an absolute maximum of 17 V. |+| 6 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V. |+| 7 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V. |+| 8 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V. |+| 9 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V. |+| 10 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V. |+| 11 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V. |+| 12 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V. |+| 13 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V. |+| 14 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V. |+| 15 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended. |+| 16 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended. |+| 17 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended. |+| 18 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended. |+| 19 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended. |+| 20 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package. |+| 21 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package. |+| 22 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package. |+| 23 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package. |+| 24 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package. |+| 25 | VBIAS | power_out | Internal bias regulator output supplying internal circuitry, nominally 2.70 V to 2.90 V with up to 100 µA static resistive load, bypassed to AGND with a 0.1 µF to 1.0 µF low-ESR ceramic capacitor. |+| 26 | REFIN | input | External reference input, a high-impedance input to the slow-start and error amplifier circuits with an input range of 0 V to 1.8 V. |+| 27 | ENA | input | Enable input; a logic high (1.40 V or greater) enables the oscillator, PWM control and MOSFET drivers, and a logic low (0.82 V or less) disables operation into a low quiescent current state, with an absolute maximum of 7 V. |+| 28 | RT | input | Frequency-setting resistor input; connect a 68 kΩ to 180 kΩ resistor to AGND to set the switching frequency from 280 kHz to 700 kHz, or leave it floating for the internal 350 kHz default. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-28-EP |+| Category | Power Supply Chip |+| Pins | 29 |++## CAD (KiCad official)++- Symbol: `TPS54672PWPR`+- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`+- 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)+- 3D model files: `tps54672pwpr-etched.step` / `tps54672pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54672pwpr.step` / `tps54672pwpr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54672) (23 pp, sha256 `9158e2ffacac2f01`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps54672pwpr-datasheet.pdf)
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connect the PowerPAD to AGND."+ },+ {+ "number": "2",+ "name": "VSENSE",+ "type": "input",+ "description": "Error amplifier inverting input, connected to the output voltage through the compensation network/output divider."+ },+ {+ "number": "3",+ "name": "COMP",+ "type": "output",+ "description": "Error amplifier output; the frequency compensation network connects from COMP to VSENSE."+ },+ {+ "number": "4",+ "name": "STATUS",+ "type": "output",+ "description": "Open-drain output that is asserted low when VIN is below the UVLO threshold, VBIAS and the internal reference are not settled, or thermal shutdown is active, and is otherwise high; sink current is limited to 10 mA absolute maximum."+ },+ {+ "number": "5",+ "name": "BOOT",+ "type": "output",+ "description": "Bootstrap output; a 0.022 µF to 0.1 µF low-ESR capacitor from BOOT to PH generates the floating drive for the high-side FET driver, with an absolute maximum of 17 V."+ },+ {+ "number": "6",+ "name": "PH",+ "type": "output",+ "description": "Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V."+ },+ {+ "number": "7",+ "name": "PH",+ "type": "output",+ "description": "Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V."+ },+ {+ "number": "8",+ "name": "PH",+ "type": "output",+ "description": "Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V."+ },+ {+ "number": "9",+ "name": "PH",+ "type": "output",+ "description": "Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V."+ },+ {+ "number": "10",+ "name": "PH",+ "type": "output",+ "description": "Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V."+ },+ {+ "number": "11",+ "name": "PH",+ "type": "output",+ "description": "Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V."+ },+ {+ "number": "12",+ "name": "PH",+ "type": "output",+ "description": "Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V."+ },+ {+ "number": "13",+ "name": "PH",+ "type": "output",+ "description": "Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V."+ },+ {+ "number": "14",+ "name": "PH",+ "type": "output",+ "description": "Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V."+ },+ {+ "number": "15",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended."+ },+ {+ "number": "16",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended."+ },+ {+ "number": "17",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended."+ },+ {+ "number": "18",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended."+ },+ {+ "number": "19",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended."+ },+ {+ "number": "20",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package."+ },+ {+ "number": "21",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package."+ },+ {+ "number": "22",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package."+ },+ {+ "number": "23",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package."+ },+ {+ "number": "24",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package."+ },+ {+ "number": "25",+ "name": "VBIAS",+ "type": "power_out",+ "description": "Internal bias regulator output supplying internal circuitry, nominally 2.70 V to 2.90 V with up to 100 µA static resistive load, bypassed to AGND with a 0.1 µF to 1.0 µF low-ESR ceramic capacitor."+ },+ {+ "number": "26",+ "name": "REFIN",+ "type": "input",+ "description": "External reference input, a high-impedance input to the slow-start and error amplifier circuits with an input range of 0 V to 1.8 V."+ },+ {+ "number": "27",+ "name": "ENA",+ "type": "input",+ "description": "Enable input; a logic high (1.40 V or greater) enables the oscillator, PWM control and MOSFET drivers, and a logic low (0.82 V or less) disables operation into a low quiescent current state, with an absolute maximum of 7 V."+ },+ {+ "number": "28",+ "name": "RT",+ "type": "input",+ "description": "Frequency-setting resistor input; connect a 68 kΩ to 180 kΩ resistor to AGND to set the switching frequency from 280 kHz to 700 kHz, or leave it floating for the internal 350 kHz default."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The PowerPAD exposed thermal pad under the package is not a numbered pin in the datasheet (it is onl; Pin types for BOOT, PH, COMP and STATUS are judgment calls mapped to KiCad ERC classes from the data; The datasheet's PIN ASSIGNMENTS (page 4) and TERMINAL FUNCTIONS (page 5) agree on pin numbers and na",+ "exposed pad 29 added from the footprint"+ ],+ "pages_sent": 23,+ "cost_usd": 0.1124,+ "at": "2026-10-08T20:46:10"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps54672",+ "pages": 23,+ "sha256": "9158e2ffacac2f01",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps54672pwpr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.2,+ 9.7,+ 1.05+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ff242f1d3be9d09e7f929707a2c5b1ee974a4f882053b04bcdb1cd2cb21223ef",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps54672pwpr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.2,+ 9.7,+ 1.05+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d73b878f8e904cdcbba4482c2cd0d31a20910ba7b829a857124bb310c15e9d27",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}