component
TPS54613PWPR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+65@@ -0,0 +1,65 @@+# TPS54613PWPR++**Texas Instruments** · DC-DC Converters · HTSSOP-28-EP++TPS54613PWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGND | power_in | Analog ground and return for the slow-start capacitor, VBIAS capacitor and RT resistor; it must be connected to the PowerPAD. |+| 2 | VSENSE | input | Error amplifier inverting input that must be connected directly to the output voltage sense point. |+| 3 | NC | unconnected | No connection. |+| 4 | PWRGD | output | Open-drain powergood output that is high-Z when VSENSE is at or above 90% of Vref and low otherwise, and is also low when SS/ENA is low or internal shutdown is active. |+| 5 | BOOT | power_out | Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating drive for the high-side FET driver. |+| 6 | PH | output | Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor. |+| 7 | PH | output | Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor. |+| 8 | PH | output | Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor. |+| 9 | PH | output | Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor. |+| 10 | PH | output | Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor. |+| 11 | PH | output | Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor. |+| 12 | PH | output | Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor. |+| 13 | PH | output | Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor. |+| 14 | PH | output | Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor. |+| 15 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |+| 16 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |+| 17 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |+| 18 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |+| 19 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |+| 20 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package. |+| 21 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package. |+| 22 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package. |+| 23 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package. |+| 24 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package. |+| 25 | VBIAS | power_out | Internal bias regulator output supplying the internal circuitry, to be bypassed to AGND with a high-quality low-ESR 0.1-µF to 1-µF ceramic capacitor; absolute maximum source current is 6 mA. |+| 26 | SS/ENA | input | Dual-function slow-start and enable pin that provides a logic input to enable or disable operation and a capacitor input to externally set the start-up time; absolute maximum voltage is 7 V. |+| 27 | FSEL | input | Frequency select logic input that chooses between two internally set switching frequencies; absolute maximum voltage is 7 V. |+| 28 | RT | input | Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency; absolute maximum voltage is 6 V. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-28-EP |+| Category | Power Supply Chip |+| Pins | 29 |++## CAD (KiCad official)++- Symbol: `TPS54613PWPR`+- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`+- 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)+- 3D model files: `tps54613pwpr-etched.step` / `tps54613pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54613pwpr.step` / `tps54613pwpr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54612) (29 pp, sha256 `c94c631e87d000c3`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps54613pwpr-datasheet.pdf)
page.jsonadded+327@@ -0,0 +1,327 @@+{+ "slug": "tps54613pwpr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "tps54613pwpr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps54613pwpr.kicad_sym",+ "tps54613pwpr.kicad_mod",+ "tps54613pwpr.glb",+ "tps54613pwpr.step",+ "tps54613pwpr.lbr",+ "docs/hero.png",+ "docs/tps54613pwpr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps54613pwpr-hero.glb",+ "tps54613pwpr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS54613PWPR",+ "manufacturer": "Texas Instruments",+ "package": "HTSSOP-28-EP",+ "pin_count": 29,+ "category": "Power Supply Chip",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps54612",+ "parts": {+ "symbol": "tps54613pwpr.kicad_sym",+ "footprint": "tps54613pwpr.kicad_mod",+ "model_3d": "tps54613pwpr-hero.glb",+ "model_3d_plain": "tps54613pwpr.glb",+ "model_3d_step": "tps54613pwpr-etched.step",+ "model_3d_step_plain": "tps54613pwpr.step",+ "lbr": "tps54613pwpr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2072905",+ "digikey": "296-TPS54613PWPRTR-ND",+ "mouser": "595-TPS54613PWPR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T23:51:51Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-TPS54613PWPRTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS54613PWPR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground and return for the slow-start capacitor, VBIAS capacitor and RT resistor; it must be connected to the PowerPAD."+ },+ {+ "number": "2",+ "name": "VSENSE",+ "type": "input",+ "description": "Error amplifier inverting input that must be connected directly to the output voltage sense point."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection."+ },+ {+ "number": "4",+ "name": "PWRGD",+ "type": "output",+ "description": "Open-drain powergood output that is high-Z when VSENSE is at or above 90% of Vref and low otherwise, and is also low when SS/ENA is low or internal shutdown is active."+ },+ {+ "number": "5",+ "name": "BOOT",+ "type": "power_out",+ "description": "Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating drive for the high-side FET driver."+ },+ {+ "number": "6",+ "name": "PH",+ "type": "output",+ "description": "Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor."+ },+ {+ "number": "7",+ "name": "PH",+ "type": "output",+ "description": "Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor."+ },+ {+ "number": "8",+ "name": "PH",+ "type": "output",+ "description": "Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor."+ },+ {+ "number": "9",+ "name": "PH",+ "type": "output",+ "description": "Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor."+ },+ {+ "number": "10",+ "name": "PH",+ "type": "output",+ "description": "Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor."+ },+ {+ "number": "11",+ "name": "PH",+ "type": "output",+ "description": "Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor."+ },+ {+ "number": "12",+ "name": "PH",+ "type": "output",+ "description": "Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor."+ },+ {+ "number": "13",+ "name": "PH",+ "type": "output",+ "description": "Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor."+ },+ {+ "number": "14",+ "name": "PH",+ "type": "output",+ "description": "Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins should be tied together and routed to the output inductor."+ },+ {+ "number": "15",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns."+ },+ {+ "number": "16",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns."+ },+ {+ "number": "17",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns."+ },+ {+ "number": "18",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns."+ },+ {+ "number": "19",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns."+ },+ {+ "number": "20",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package."+ },+ {+ "number": "21",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package."+ },+ {+ "number": "22",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package."+ },+ {+ "number": "23",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package."+ },+ {+ "number": "24",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package."+ },+ {+ "number": "25",+ "name": "VBIAS",+ "type": "power_out",+ "description": "Internal bias regulator output supplying the internal circuitry, to be bypassed to AGND with a high-quality low-ESR 0.1-µF to 1-µF ceramic capacitor; absolute maximum source current is 6 mA."+ },+ {+ "number": "26",+ "name": "SS/ENA",+ "type": "input",+ "description": "Dual-function slow-start and enable pin that provides a logic input to enable or disable operation and a capacitor input to externally set the start-up time; absolute maximum voltage is 7 V."+ },+ {+ "number": "27",+ "name": "FSEL",+ "type": "input",+ "description": "Frequency select logic input that chooses between two internally set switching frequencies; absolute maximum voltage is 7 V."+ },+ {+ "number": "28",+ "name": "RT",+ "type": "input",+ "description": "Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency; absolute maximum voltage is 6 V."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The HTSSOP PowerPAD (exposed thermal pad) is not given a pin number in the datasheet text, so it is ; Pin numbers were taken from the pin table on page 3 and cross-checked against the top-view diagram: ; Pin types are KiCad ERC mappings based on the datasheet type codes and descriptions. BOOT and VBIAS ",+ "exposed pad 29 added from the footprint"+ ],+ "pages_sent": 11,+ "cost_usd": 0.0897,+ "at": "2026-10-07T23:51:36"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps54612",+ "pages": 29,+ "sha256": "c94c631e87d000c3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps54613pwpr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.2,+ 9.7,+ 1.05+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ff242f1d3be9d09e7f929707a2c5b1ee974a4f882053b04bcdb1cd2cb21223ef",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps54613pwpr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.2,+ 9.7,+ 1.05+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7d526b93baad0179c158a86ac81560d208ee6d91877a047445b9ca01299270d9",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}