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TPS54362BQPWPRQ1
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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+57@@ -0,0 +1,57 @@+# TPS54362BQPWPRQ1++**Texas Instruments** · DC-DC Converters · HTSSOP-20-EP++TPS54362BQPWPRQ1 from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NU | passive | Pin table says to connect this pin to ground, while the pin-configuration legend defines NU as make no external connection, so confirm before layout. |+| 2 | NU | unconnected | Not used; the pin-configuration legend states NU pins make no external connection. |+| 3 | SYNC | input | External synchronization clock input that overrides the internal oscillator clock, with an internal 62 kΩ (typical) pulldown to ground. |+| 4 | LPM | input | Low-power mode control driven by a digital input signal, with an internal 62 kΩ (typical) pulldown to ground. |+| 5 | EN | input | Enable pin, internally pulled up, that requires an external pullup or pulldown to enable or disable the device. |+| 6 | RT | output | External resistor to ground programs the internal oscillator frequency. |+| 7 | Rslew | output | External resistor to ground controls the slew rate of the internal switching FET. |+| 8 | RST | output | Active-low, open-drain reset output that connects to an external bias voltage through a resistor and is asserted high after the device starts regulating. |+| 9 | Cdly | bidirectional | External capacitor to ground programs the power-on-reset delay. |+| 10 | GND | power_in | Ground pin. |+| 11 | SS | bidirectional | External capacitor to ground programs the soft-start time. |+| 12 | OV_TH | input | Overvoltage sense input that monitors the regulated output as divided by the external resistor network between VReg and ground, which sets the threshold. |+| 13 | RST_TH | input | Undervoltage and reset sense input that monitors the regulated output as divided by the external resistor network between VReg and ground, which sets the threshold that initiates a reset-output signal. |+| 14 | VSENSE | input | Inverting node of the error amplifier for voltage-mode control. |+| 15 | COMP | bidirectional | Error-amplifier output that connects to external compensation components. |+| 16 | VReg | input | Internal low-side FET connection to load the output during start-up or to limit overshoot. |+| 17 | PH | output | Source of the internal switching FET. |+| 18 | VIN | power_in | Unregulated input voltage; pin 18 and pin 19 must be connected together externally. |+| 19 | VIN | power_in | Unregulated input voltage; pin 19 must be connected together with pin 18 externally. |+| 20 | BOOT | output | External bootstrap capacitor connects from BOOT to PH to drive the gate of the internal switching FET. |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-20-EP |+| Category | Power Management (PMIC) |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `TPS54362BQPWPRQ1`+- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`+- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `tps54362bqpwprq1-etched.step` / `tps54362bqpwprq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54362bqpwprq1.step` / `tps54362bqpwprq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54362-q1) (44 pp, sha256 `81197f9afad901c9`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps54362bqpwprq1-datasheet.pdf)
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the pin-configuration legend states NU pins make no external connection."+ },+ {+ "number": "3",+ "name": "SYNC",+ "type": "input",+ "description": "External synchronization clock input that overrides the internal oscillator clock, with an internal 62 kΩ (typical) pulldown to ground."+ },+ {+ "number": "4",+ "name": "LPM",+ "type": "input",+ "description": "Low-power mode control driven by a digital input signal, with an internal 62 kΩ (typical) pulldown to ground."+ },+ {+ "number": "5",+ "name": "EN",+ "type": "input",+ "description": "Enable pin, internally pulled up, that requires an external pullup or pulldown to enable or disable the device."+ },+ {+ "number": "6",+ "name": "RT",+ "type": "output",+ "description": "External resistor to ground programs the internal oscillator frequency."+ },+ {+ "number": "7",+ "name": "Rslew",+ "type": "output",+ "description": "External resistor to ground controls the slew rate of the internal switching FET."+ },+ {+ "number": "8",+ "name": "RST",+ "type": "output",+ "description": "Active-low, open-drain reset output that connects to an external bias voltage through a resistor and is asserted high after the device starts regulating."+ },+ {+ "number": "9",+ "name": "Cdly",+ "type": "bidirectional",+ "description": "External capacitor to ground programs the power-on-reset delay."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin."+ },+ {+ "number": "11",+ "name": "SS",+ "type": "bidirectional",+ "description": "External capacitor to ground programs the soft-start time."+ },+ {+ "number": "12",+ "name": "OV_TH",+ "type": "input",+ "description": "Overvoltage sense input that monitors the regulated output as divided by the external resistor network between VReg and ground, which sets the threshold."+ },+ {+ "number": "13",+ "name": "RST_TH",+ "type": "input",+ "description": "Undervoltage and reset sense input that monitors the regulated output as divided by the external resistor network between VReg and ground, which sets the threshold that initiates a reset-output signal."+ },+ {+ "number": "14",+ "name": "VSENSE",+ "type": "input",+ "description": "Inverting node of the error amplifier for voltage-mode control."+ },+ {+ "number": "15",+ "name": "COMP",+ "type": "bidirectional",+ "description": "Error-amplifier output that connects to external compensation components."+ },+ {+ "number": "16",+ "name": "VReg",+ "type": "input",+ "description": "Internal low-side FET connection to load the output during start-up or to limit overshoot."+ },+ {+ "number": "17",+ "name": "PH",+ "type": "output",+ "description": "Source of the internal switching FET."+ },+ {+ "number": "18",+ "name": "VIN",+ "type": "power_in",+ "description": "Unregulated input voltage; pin 18 and pin 19 must be connected together externally."+ },+ {+ "number": "19",+ "name": "VIN",+ "type": "power_in",+ "description": "Unregulated input voltage; pin 19 must be connected together with pin 18 externally."+ },+ {+ "number": "20",+ "name": "BOOT",+ "type": "output",+ "description": "External bootstrap capacitor connects from BOOT to PH to drive the gate of the internal switching FET."+ },+ {+ "number": "21",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin 1 is described as 'Connect to ground' in the pin-function table but the NU legend says 'Make no ; Pin 2 has no row in the pin-function table. It was assigned NU/unconnected because the pin-configura; The pin-function table lists GND (pin 10) as direction O. It was typed as power_in per the KiCad con",+ "exposed pad 21 added from the footprint"+ ],+ "pages_sent": 11,+ "cost_usd": 0.0816,+ "at": "2026-10-08T02:32:46"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps54362-q1",+ "pages": 44,+ "sha256": "81197f9afad901c9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps54362bqpwprq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8d83801c5d0e7a05217d2292ee8253b2ac4e657d44931722ec0bd2d19987b534",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps54362bqpwprq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8cc027e49c8d6fc0356bd4f135aff50627abff9f008c791ff789b41a44d974f3",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}