component
TPS54352PWPR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+53@@ -0,0 +1,53 @@+# TPS54352PWPR++**Texas Instruments** · DC-DC Converters · HTSSOP-16-EP++TPS54352PWPR from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VIN | power_in | Input supply voltage, 4.5 V to 20 V; must be bypassed with a low ESR 10-µF ceramic capacitor placed as close to the device as possible (pins 1 and 2 are both VIN). |+| 2 | VIN | power_in | Input supply voltage, 4.5 V to 20 V; must be bypassed with a low ESR 10-µF ceramic capacitor placed as close to the device as possible (pins 1 and 2 are both VIN). |+| 3 | UVLO | input | Undervoltage lockout pin; an external resistive divider from VIN overrides the internal default VIN start and stop thresholds (never connect directly to VIN). |+| 4 | PWRGD | output | Open-drain power good output; a low indicates the output is below the desired output voltage, with an internal rising edge filter on the comparator output. |+| 5 | RT | input | Frequency setting pin; a resistor from RT to AGND sets the switching frequency, while grounding or floating it selects an internally preselected frequency (250 kHz grounded, 500 kHz floating). |+| 6 | SYNC | bidirectional | Bidirectional synchronization I/O; output when RT is floating or low, input on a falling edge signal when an RT resistor is used, and a 10 kΩ resistor must always be tied from SYNC to ground. |+| 7 | ENA | input | Enable pin; below 0.5 V the device stops switching, and floating the pin enables the device. |+| 8 | COMP | passive | Error amplifier output; do not connect anything to this pin. |+| 9 | VSENSE | input | Feedback pin (error amplifier inverting input). |+| 10 | AGND | power_in | Analog ground internally connected to the sensitive analog ground circuitry; connect to PGND and PowerPAD. |+| 11 | PGND | power_in | Power ground, the noisy internal ground carrying LSG driver return currents; connect to AGND and PowerPAD. |+| 12 | VBIAS | power_out | Internal 8.0-V bias voltage requiring a 1.0-µF ceramic bypass capacitor, with up to 1 mA available for external use. |+| 13 | LSG | output | Gate drive for the optional low side n-channel MOSFET; otherwise leave open and connect a schottky diode from ground to PH. |+| 14 | PH | output | Phase node; connect to the external L-C filter (pins 14 and 15 are both PH). |+| 15 | PH | output | Phase node; connect to the external L-C filter (pins 14 and 15 are both PH). |+| 16 | BOOT | passive | Bootstrap capacitor for the high side gate driver; connect a 0.1-µF ceramic capacitor from BOOT to PH. |+| 17 | PowerPAD | power_in | Exposed thermal pad; PGND and AGND pins must be connected to it for proper operation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-16-EP |+| Category | Power Supply Chip |+| Pins | 17 |++## CAD (KiCad official)++- Symbol: `TPS54352PWPR`+- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`+- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)+- 3D model files: `tps54352pwpr-etched.step` / `tps54352pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54352pwpr.step` / `tps54352pwpr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54356) (37 pp, sha256 `1e7f079dce00c4b2`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps54352pwpr-datasheet.pdf)
page.jsonadded+255@@ -0,0 +1,255 @@+{+ "slug": "tps54352pwpr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "tps54352pwpr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps54352pwpr.kicad_sym",+ "tps54352pwpr.kicad_mod",+ "tps54352pwpr.glb",+ "tps54352pwpr.step",+ "tps54352pwpr.lbr",+ "docs/hero.png",+ "docs/tps54352pwpr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps54352pwpr-hero.glb",+ "tps54352pwpr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS54352PWPR",+ "manufacturer": "Texas Instruments",+ "package": "HTSSOP-16-EP",+ "pin_count": 17,+ "category": "Power Supply Chip",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps54356",+ "parts": {+ "symbol": "tps54352pwpr.kicad_sym",+ "footprint": "tps54352pwpr.kicad_mod",+ "model_3d": "tps54352pwpr-hero.glb",+ "model_3d_plain": "tps54352pwpr.glb",+ "model_3d_step": "tps54352pwpr-etched.step",+ "model_3d_step_plain": "tps54352pwpr.step",+ "lbr": "tps54352pwpr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2072793",+ "digikey": "TPS54352PWPR-ND",+ "mouser": "595-TPS54352PWPR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:32:49Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "TPS54352PWPR-ND",+ "status": "found",+ "lifecycle": "Obsolete"+ },+ "mouser": {+ "pn": "595-TPS54352PWPR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply voltage, 4.5 V to 20 V; must be bypassed with a low ESR 10-µF ceramic capacitor placed as close to the device as possible (pins 1 and 2 are both VIN)."+ },+ {+ "number": "2",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply voltage, 4.5 V to 20 V; must be bypassed with a low ESR 10-µF ceramic capacitor placed as close to the device as possible (pins 1 and 2 are both VIN)."+ },+ {+ "number": "3",+ "name": "UVLO",+ "type": "input",+ "description": "Undervoltage lockout pin; an external resistive divider from VIN overrides the internal default VIN start and stop thresholds (never connect directly to VIN)."+ },+ {+ "number": "4",+ "name": "PWRGD",+ "type": "output",+ "description": "Open-drain power good output; a low indicates the output is below the desired output voltage, with an internal rising edge filter on the comparator output."+ },+ {+ "number": "5",+ "name": "RT",+ "type": "input",+ "description": "Frequency setting pin; a resistor from RT to AGND sets the switching frequency, while grounding or floating it selects an internally preselected frequency (250 kHz grounded, 500 kHz floating)."+ },+ {+ "number": "6",+ "name": "SYNC",+ "type": "bidirectional",+ "description": "Bidirectional synchronization I/O; output when RT is floating or low, input on a falling edge signal when an RT resistor is used, and a 10 kΩ resistor must always be tied from SYNC to ground."+ },+ {+ "number": "7",+ "name": "ENA",+ "type": "input",+ "description": "Enable pin; below 0.5 V the device stops switching, and floating the pin enables the device."+ },+ {+ "number": "8",+ "name": "COMP",+ "type": "passive",+ "description": "Error amplifier output; do not connect anything to this pin."+ },+ {+ "number": "9",+ "name": "VSENSE",+ "type": "input",+ "description": "Feedback pin (error amplifier inverting input)."+ },+ {+ "number": "10",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground internally connected to the sensitive analog ground circuitry; connect to PGND and PowerPAD."+ },+ {+ "number": "11",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground, the noisy internal ground carrying LSG driver return currents; connect to AGND and PowerPAD."+ },+ {+ "number": "12",+ "name": "VBIAS",+ "type": "power_out",+ "description": "Internal 8.0-V bias voltage requiring a 1.0-µF ceramic bypass capacitor, with up to 1 mA available for external use."+ },+ {+ "number": "13",+ "name": "LSG",+ "type": "output",+ "description": "Gate drive for the optional low side n-channel MOSFET; otherwise leave open and connect a schottky diode from ground to PH."+ },+ {+ "number": "14",+ "name": "PH",+ "type": "output",+ "description": "Phase node; connect to the external L-C filter (pins 14 and 15 are both PH)."+ },+ {+ "number": "15",+ "name": "PH",+ "type": "output",+ "description": "Phase node; connect to the external L-C filter (pins 14 and 15 are both PH)."+ },+ {+ "number": "16",+ "name": "BOOT",+ "type": "passive",+ "description": "Bootstrap capacitor for the high side gate driver; connect a 0.1-µF ceramic capacitor from BOOT to PH."+ },+ {+ "number": "17",+ "name": "PowerPAD",+ "type": "power_in",+ "description": "Exposed thermal pad; PGND and AGND pins must be connected to it for proper operation."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The PowerPAD exposed thermal pad is not given a pin number in the datasheet text, so it is omitted f; The pinout is taken from the TPS5435x family pin table on page 7, which is shared by all TPS5435x va",+ "exposed pad 17 added from the footprint"+ ],+ "pages_sent": 13,+ "cost_usd": 0.084,+ "at": "2026-10-08T15:32:27"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps54356",+ "pages": 37,+ "sha256": "1e7f079dce00c4b2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps54352pwpr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7982746831c0bd23f4690608869ad67776faae5c762fb0376666126a3998921b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps54352pwpr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "57ac52c92a439122974c331d10f121e562482f97e10db4c022a0c01d955cc9b7",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}