TPS54331 - Commit - Adom Wiki

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tps54331: backfill missing artifacts (etch, variants)

Ray ·a001b5eb1d ·2mo ago ·parent 9c9538e

3 files changed +22200−5 diff truncated

README.md+2 page.json+16−5 tps54331-etched.step+22182

README.md+2

@@ -32,6 +32,8 @@ A 3 A step-down (buck) DC-DC converter with the high-side switch integrated, in  ## Ordering variants +Same part, different packaging or reel option.+ - `TPS54331DR (SOIC-8)` - `TPS54331D (SOIC-8, tube)`

page.json+16−5

@@ -36,7 +36,7 @@         "number": "1",         "name": "BOOT",         "type": "power_out",-        "description": "Bootstrap capacitor node for the internal high-side N-channel MOSFET gate driver. A 0.1-\u00b5F ceramic capacitor is required between BOOT and PH. Absolute-max BOOT-to-GND is 38 V and BOOT-PH is 8 V; if the BOOT-PH voltage falls below the minimum, the high-side MOSFET is turned off until the bootstrap cap is refreshed."+        "description": "Bootstrap capacitor node for the internal high-side N-channel MOSFET gate driver. A 0.1-µF ceramic capacitor is required between BOOT and PH. Absolute-max BOOT-to-GND is 38 V and BOOT-PH is 8 V; if the BOOT-PH voltage falls below the minimum, the high-side MOSFET is turned off until the bootstrap cap is refreshed."       },       {         "number": "2",@@ -48,13 +48,13 @@         "number": "3",         "name": "EN",         "type": "input",-        "description": "Enable input. Float to enable; pull below 1.25 V (typ enable threshold) to disable. A resistor divider from VIN to EN to GND programs the input UVLO with two resistors (uses the small hysteresis current, ~-1 \u00b5A at threshold and ~-4 \u00b5A at threshold+50 mV). Absolute-max 6 V."+        "description": "Enable input. Float to enable; pull below 1.25 V (typ enable threshold) to disable. A resistor divider from VIN to EN to GND programs the input UVLO with two resistors (uses the small hysteresis current, ~-1 µA at threshold and ~-4 µA at threshold+50 mV). Absolute-max 6 V."       },       {         "number": "4",         "name": "SS",         "type": "input",-        "description": "Slow-start pin. An external capacitor from SS to GND sets the output voltage rise time (charge current ~2 \u00b5A at V(SS)=0.4 V). SS-to-VSENSE matching typ 10 mV. Absolute-max 3 V."+        "description": "Slow-start pin. An external capacitor from SS to GND sets the output voltage rise time (charge current ~2 µA at V(SS)=0.4 V). SS-to-VSENSE matching typ 10 mV. Absolute-max 3 V."       },       {         "number": "5",@@ -66,7 +66,7 @@         "number": "6",         "name": "COMP",         "type": "output",-        "description": "Error-amplifier output and input to the PWM comparator. Connect the type-II frequency compensation network (typically Rc + Cc series to GND with optional high-frequency Cp) to this pin. Error-amp gm 92 \u00b5mhos, \u00b17 \u00b5A source/sink typ. Absolute-max 3 V."+        "description": "Error-amplifier output and input to the PWM comparator. Connect the type-II frequency compensation network (typically Rc + Cc series to GND with optional high-frequency Cp) to this pin. Error-amp gm 92 µmhos, ±7 µA source/sink typ. Absolute-max 3 V."       },       {         "number": "7",@@ -148,6 +148,17 @@     "docs/hero.png",     "docs/tps54331-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"+    "viewers/footprint.html",+    "tps54331-etched.step"+  ],+  "variants": [+    {+      "mpn": "TPS54331DR (SOIC-8)",+      "kind": "packaging"+    },+    {+      "mpn": "TPS54331D (SOIC-8, tube)",+      "kind": "packaging"+    }   ] }\ No newline at end of file

tps54331-etched.stepadded+22182

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CURVE() GEOMETRIC_REPRESENTATION_ITEM() +RATIONAL_B_SPLINE_CURVE((1.,0.5,1.,0.5,1.,0.5,1.)) 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