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Set visibility: public

Ray ·6827680806 ·9d ago ·parent 06dfa6e
1 file changed +11−8
page.json+11−8
@@ -59,13 +59,13 @@         "number": "2",         "name": "VREG5",         "type": "power_out",-        "description": "Internal 5.5-V LDO power supply output; connect a 1-\u00b5F ceramic capacitor to GND; output voltage 5.3-5.7 V, max output current 70 mA."+        "description": "Internal 5.5-V LDO power supply output; connect a 1-µF ceramic capacitor to GND; output voltage 5.3-5.7 V, max output current 70 mA."       },       {         "number": "3",         "name": "SS",         "type": "bidirectional",-        "description": "Soft-start control pin; connect an external capacitor to GND to set soft-start time; charge current 1.4-2.6 \u00b5A, discharge current 0.1-0.2 mA."+        "description": "Soft-start control pin; connect an external capacitor to GND to set soft-start time; charge current 1.4-2.6 µA, discharge current 0.1-0.2 mA."       },       {         "number": "4",@@ -77,13 +77,13 @@         "number": "5",         "name": "PG",         "type": "output",-        "description": "Open-drain power-good output; asserts high when VFB is within \u00b110% of target; sink current 2.5-5.0 mA at VPG = 0.5 V."+        "description": "Open-drain power-good output; asserts high when VFB is within ±10% of target; sink current 2.5-5.0 mA at VPG = 0.5 V."       },       {         "number": "6",         "name": "EN",         "type": "input",-        "description": "Enable control input; logic high (\u22651.5 V) enables the converter, logic low (\u22640.4 V) shuts it down; max input voltage 18 V."+        "description": "Enable control input; logic high (≥1.5 V) enables the converter, logic low (≤0.4 V) shuts it down; max input voltage 18 V."       },       {         "number": "7",@@ -119,7 +119,7 @@         "number": "12",         "name": "VBST",         "type": "power_in",-        "description": "Bootstrap supply input for high-side N-channel FET gate driver; connect a 0.1-\u00b5F ceramic capacitor from this pin to SW; internal PN diode from VREG5 to VBST; max voltage 26 V (abs), 5.7 V with respect to SW (recommended)."+        "description": "Bootstrap supply input for high-side N-channel FET gate driver; connect a 0.1-µF ceramic capacitor from this pin to SW; internal PN diode from VREG5 to VBST; max voltage 26 V (abs), 5.7 V with respect to SW (recommended)."       },       {         "number": "13",@@ -137,7 +137,7 @@         "number": "15",         "name": "VCC",         "type": "power_in",-        "description": "Supply input for internal 5-V linear regulator for control circuitry; recommended operating range 4.5-18.0 V; operating supply current 850-1300 \u00b5A, shutdown current <10 \u00b5A."+        "description": "Supply input for internal 5-V linear regulator for control circuitry; recommended operating range 4.5-18.0 V; operating supply current 850-1300 µA, shutdown current <10 µA."       },       {         "number": "16",@@ -149,7 +149,7 @@         "number": "17",         "name": "PowerPAD",         "type": "power_in",-        "description": "Exposed thermal pad; must be soldered to PCB for thermal and mechanical performance; must be connected to PGND; \u03b8JCbot = 3.9 \u00b0C/W."+        "description": "Exposed thermal pad; must be soldered to PCB for thermal and mechanical performance; must be connected to PGND; θJCbot = 3.9 °C/W."       }     ],     "provenance": {@@ -230,5 +230,8 @@     "docs/tps53511rgtr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file