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TPS40428RHAT
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Texas Instruments AC-DC Controllers And Regulators, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# TPS40428RHAT++**Texas Instruments** · AC-DC Controllers And Regulators · VQFN-40-EP(6x6)++TPS40428RHAT from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SYNC | bidirectional | Synchronization pin for external clock input; clock frequency must be 4 times switching frequency for 1-, 2-, or 4-phase operation, or 3 times for 3-phase operation. |+| 2 | PHSET | bidirectional | Phase set pin for multiphase mode configuration; pulled up to BP5 via internal resistor when floating. |+| 3 | CNTL1 | input | Logic level input which starts or stops channel 1; internal 6-µA current source pulls VCNTL1 up to VBP5 when floating. |+| 4 | CNTL2 | input | Logic level input which starts or stops channel 2; internal 6-µA current source pulls VCNTL2 up to VBP5 when floating. |+| 5 | SMBALERT | output | PMBus alert pin with open-drain output to signal fault or warning conditions to host system. |+| 6 | PMBDATA | bidirectional | PMBus data pin for serial communication between controller and host; open-drain output. |+| 7 | PMBCLK | input | PMBus clock pin for serial communication synchronization at 100 kHz or 400 kHz. |+| 8 | AGND | power_in | Analog ground pin used for analog signal return paths; connect to thermal pad directly. |+| 9 | AVSDATA | input | AVS data pin for adaptive voltage scaling communication with ASIC at 1.8V or 2.5V logic levels. |+| 10 | AVSCLK | input | AVS clock pin for timing adaptive voltage scaling data communication at 10 MHz to 30 MHz. |+| 11 | ADDR1 | input | High-order address pin for PMBus device identification; connect E96 series resistor to AGND. |+| 12 | ADDR0 | input | Low-order address pin for PMBus device identification; connect E96 series resistor to AGND. |+| 13 | GSNS2 | input | Negative pin of voltage sense signal for channel 2 output. |+| 14 | VSNS2 | input | Positive pin of voltage sense signal for channel 2 output. |+| 15 | COMP2 | output | Output of error amplifier 2 for channel 2; connection node for feedback compensation components. |+| 16 | FB2 | input | Inverting input to error amplifier 2; in normal operation, voltage equals 0.6V internal reference. |+| 17 | FLT2 | bidirectional | Fault signal pin for channel 2 with internal 100-kΩ resistor pulling to BP3. |+| 18 | CS2N | input | Negative pin of current sense amplifier for channel 2; internal 4-kΩ resistor pulls to 1.24V during smart power mode. |+| 19 | CS2P | input | Positive pin of current sense amplifier for channel 2. |+| 20 | TSNS2 | input | External temperature sense signal input for channel 2. |+| 21 | ISH2 | input | Current sharing signal of channel 2 for multi-phase mode current balancing. |+| 22 | PG2 | output | Open-drain power good indicator for channel 2 output voltage; pulled to ground internally in slave mode. |+| 23 | PWM2 | output | PWM signal output for channel 2 with three levels: high (high-side MOSFET on), low (low-side on), or tri-state (both off). |+| 24 | VDD | power_in | Power input to controller with operating voltage range 4.5V to 20V; bypass with 1µF minimum low-ESR ceramic capacitor to AGND. |+| 25 | BP5 | power_out | Regulated 5V output from internal regulator; bypass with 1µF minimum low-ESR ceramic capacitor to PGND. |+| 26 | BP3 | power_out | Regulated 3.3V output for logic bias; bypass with 0.33µF minimum low-ESR ceramic capacitor to AGND. |+| 27 | PGND | power_in | Power ground pin for power return paths and BP5 bypass capacitor; connect to thermal pad directly. |+| 28 | PWM1 | output | PWM signal output for channel 1 with three levels: high (high-side MOSFET on), low (low-side on), or tri-state (both off). |+| 29 | PG1 | output | Open-drain power good indicator for channel 1 output voltage; pulled to ground internally in slave mode. |+| 30 | ISH1 | input | Current sharing signal of channel 1 for multi-phase mode current balancing. |+| 31 | TSNS1 | input | External temperature sense signal input for channel 1. |+| 32 | CS1P | input | Positive pin of current sense amplifier for channel 1. |+| 33 | CS1N | input | Negative pin of current sense amplifier for channel 1; internal 4-kΩ resistor pulls to 1.24V during smart power mode. |+| 34 | FLT1 | bidirectional | Fault signal pin for channel 1 with internal 100-kΩ resistor pulling to BP3. |+| 35 | FB1 | input | Inverting input to error amplifier 1; in normal operation, voltage equals 0.6V internal reference. |+| 36 | COMP1 | output | Output of error amplifier 1 for channel 1; connection node for feedback compensation components. |+| 37 | VSNS1 | input | Positive pin of voltage sense signal for channel 1 output. |+| 38 | GSNS1 | input | Negative pin of voltage sense signal for channel 1 output. |+| 39 | DIFFO1 | output | Remote sense amplifier output for channel 1 with maximum output voltage 4.7V; compensates parasitic offset in voltage sensing. |+| 40 | RT | input | Timing resistor pin; connecting resistor from this pin to AGND sets switching frequency from 200kHz to 1.5MHz per Equation 1. |+| 41 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-40-EP(6x6) |+| Category | Power Management (PMIC) |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `TPS40428RHAT`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `tps40428rhat-etched.step` / `tps40428rhat-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps40428rhat.step` / `tps40428rhat.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps40428) (93 pp, sha256 `1bd735b7038c2f8d`, retrieved 2026-09-27, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps40428rhat-datasheet.pdf)
page.jsonadded+356@@ -0,0 +1,356 @@+{+ "slug": "tps40428rhat",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments AC-DC Controllers And Regulators, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps40428rhat",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps40428rhat.kicad_sym",+ "tps40428rhat.kicad_mod",+ "tps40428rhat.glb",+ "tps40428rhat.step",+ "tps40428rhat.lbr",+ "docs/hero.png",+ "docs/tps40428rhat-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "TPS40428RHAT",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Power Management (PMIC)",+ "subcategory": "AC-DC Controllers And Regulators",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps40428",+ "parts": {+ "symbol": "tps40428rhat.kicad_sym",+ "footprint": "tps40428rhat.kicad_mod",+ "model_3d": "tps40428rhat-etched.glb",+ "model_3d_plain": "tps40428rhat.glb",+ "model_3d_step": "tps40428rhat-etched.step",+ "model_3d_step_plain": "tps40428rhat.step",+ "lbr": "tps40428rhat.lbr"+ },+ "distributor_links": {+ "lcsc": "C181645",+ "digikey": "296-38349-2-ND",+ "mouser": "595-TPS40428RHAT"+ },+ "distributor_check": {+ "checked_at": "2026-09-27T00:32:07Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-38349-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS40428RHAT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SYNC",+ "type": "bidirectional",+ "description": "Synchronization pin for external clock input; clock frequency must be 4 times switching frequency for 1-, 2-, or 4-phase operation, or 3 times for 3-phase operation."+ },+ {+ "number": "2",+ "name": "PHSET",+ "type": "bidirectional",+ "description": "Phase set pin for multiphase mode configuration; pulled up to BP5 via internal resistor when floating."+ },+ {+ "number": "3",+ "name": "CNTL1",+ "type": "input",+ "description": "Logic level input which starts or stops channel 1; internal 6-µA current source pulls VCNTL1 up to VBP5 when floating."+ },+ {+ "number": "4",+ "name": "CNTL2",+ "type": "input",+ "description": "Logic level input which starts or stops channel 2; internal 6-µA current source pulls VCNTL2 up to VBP5 when floating."+ },+ {+ "number": "5",+ "name": "SMBALERT",+ "type": "output",+ "description": "PMBus alert pin with open-drain output to signal fault or warning conditions to host system."+ },+ {+ "number": "6",+ "name": "PMBDATA",+ "type": "bidirectional",+ "description": "PMBus data pin for serial communication between controller and host; open-drain output."+ },+ {+ "number": "7",+ "name": "PMBCLK",+ "type": "input",+ "description": "PMBus clock pin for serial communication synchronization at 100 kHz or 400 kHz."+ },+ {+ "number": "8",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground pin used for analog signal return paths; connect to thermal pad directly."+ },+ {+ "number": "9",+ "name": "AVSDATA",+ "type": "input",+ "description": "AVS data pin for adaptive voltage scaling communication with ASIC at 1.8V or 2.5V logic levels."+ },+ {+ "number": "10",+ "name": "AVSCLK",+ "type": "input",+ "description": "AVS clock pin for timing adaptive voltage scaling data communication at 10 MHz to 30 MHz."+ },+ {+ "number": "11",+ "name": "ADDR1",+ "type": "input",+ "description": "High-order address pin for PMBus device identification; connect E96 series resistor to AGND."+ },+ {+ "number": "12",+ "name": "ADDR0",+ "type": "input",+ "description": "Low-order address pin for PMBus device identification; connect E96 series resistor to AGND."+ },+ {+ "number": "13",+ "name": "GSNS2",+ "type": "input",+ "description": "Negative pin of voltage sense signal for channel 2 output."+ },+ {+ "number": "14",+ "name": "VSNS2",+ "type": "input",+ "description": "Positive pin of voltage sense signal for channel 2 output."+ },+ {+ "number": "15",+ "name": "COMP2",+ "type": "output",+ "description": "Output of error amplifier 2 for channel 2; connection node for feedback compensation components."+ },+ {+ "number": "16",+ "name": "FB2",+ "type": "input",+ "description": "Inverting input to error amplifier 2; in normal operation, voltage equals 0.6V internal reference."+ },+ {+ "number": "17",+ "name": "FLT2",+ "type": "bidirectional",+ "description": "Fault signal pin for channel 2 with internal 100-kΩ resistor pulling to BP3."+ },+ {+ "number": "18",+ "name": "CS2N",+ "type": "input",+ "description": "Negative pin of current sense amplifier for channel 2; internal 4-kΩ resistor pulls to 1.24V during smart power mode."+ },+ {+ "number": "19",+ "name": "CS2P",+ "type": "input",+ "description": "Positive pin of current sense amplifier for channel 2."+ },+ {+ "number": "20",+ "name": "TSNS2",+ "type": "input",+ "description": "External temperature sense signal input for channel 2."+ },+ {+ "number": "21",+ "name": "ISH2",+ "type": "input",+ "description": "Current sharing signal of channel 2 for multi-phase mode current balancing."+ },+ {+ "number": "22",+ "name": "PG2",+ "type": "output",+ "description": "Open-drain power good indicator for channel 2 output voltage; pulled to ground internally in slave mode."+ },+ {+ "number": "23",+ "name": "PWM2",+ "type": "output",+ "description": "PWM signal output for channel 2 with three levels: high (high-side MOSFET on), low (low-side on), or tri-state (both off)."+ },+ {+ "number": "24",+ "name": "VDD",+ "type": "power_in",+ "description": "Power input to controller with operating voltage range 4.5V to 20V; bypass with 1µF minimum low-ESR ceramic capacitor to AGND."+ },+ {+ "number": "25",+ "name": "BP5",+ "type": "power_out",+ "description": "Regulated 5V output from internal regulator; bypass with 1µF minimum low-ESR ceramic capacitor to PGND."+ },+ {+ "number": "26",+ "name": "BP3",+ "type": "power_out",+ "description": "Regulated 3.3V output for logic bias; bypass with 0.33µF minimum low-ESR ceramic capacitor to AGND."+ },+ {+ "number": "27",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground pin for power return paths and BP5 bypass capacitor; connect to thermal pad directly."+ },+ {+ "number": "28",+ "name": "PWM1",+ "type": "output",+ "description": "PWM signal output for channel 1 with three levels: high (high-side MOSFET on), low (low-side on), or tri-state (both off)."+ },+ {+ "number": "29",+ "name": "PG1",+ "type": "output",+ "description": "Open-drain power good indicator for channel 1 output voltage; pulled to ground internally in slave mode."+ },+ {+ "number": "30",+ "name": "ISH1",+ "type": "input",+ "description": "Current sharing signal of channel 1 for multi-phase mode current balancing."+ },+ {+ "number": "31",+ "name": "TSNS1",+ "type": "input",+ "description": "External temperature sense signal input for channel 1."+ },+ {+ "number": "32",+ "name": "CS1P",+ "type": "input",+ "description": "Positive pin of current sense amplifier for channel 1."+ },+ {+ "number": "33",+ "name": "CS1N",+ "type": "input",+ "description": "Negative pin of current sense amplifier for channel 1; internal 4-kΩ resistor pulls to 1.24V during smart power mode."+ },+ {+ "number": "34",+ "name": "FLT1",+ "type": "bidirectional",+ "description": "Fault signal pin for channel 1 with internal 100-kΩ resistor pulling to BP3."+ },+ {+ "number": "35",+ "name": "FB1",+ "type": "input",+ "description": "Inverting input to error amplifier 1; in normal operation, voltage equals 0.6V internal reference."+ },+ {+ "number": "36",+ "name": "COMP1",+ "type": "output",+ "description": "Output of error amplifier 1 for channel 1; connection node for feedback compensation components."+ },+ {+ "number": "37",+ "name": "VSNS1",+ "type": "input",+ "description": "Positive pin of voltage sense signal for channel 1 output."+ },+ {+ "number": "38",+ "name": "GSNS1",+ "type": "input",+ "description": "Negative pin of voltage sense signal for channel 1 output."+ },+ {+ "number": "39",+ "name": "DIFFO1",+ "type": "output",+ "description": "Remote sense amplifier output for channel 1 with maximum output voltage 4.7V; compensates parasitic offset in voltage sensing."+ },+ {+ "number": "40",+ "name": "RT",+ "type": "input",+ "description": "Timing resistor pin; connecting resistor from this pin to AGND sets switching frequency from 200kHz to 1.5MHz per Equation 1."+ },+ {+ "number": "41",+ "name": "PAD",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 93,+ "cost_usd": 0.8397,+ "at": "2026-09-27T00:31:48"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps40428",+ "pages": 93,+ "sha256": "1bd735b7038c2f8d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}