TPS3808G01DBVR

@@ -26,13 +26,16 @@       "model_3d_step": "tps3808g01dbvr.step",       "lbr": "tps3808g01dbvr.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "digikey": "296-17188-2-ND",+      "lcsc": "C19653"+    },     "pins": [       {         "number": "1",         "name": "RESET",         "type": "output",-        "description": "Active-low, open-drain RESET output. Driven low when SENSE < VIT or MR is low, and remains asserted for the programmed reset delay (td) after both conditions clear. Requires an external pull-up (10 kΩ to 1 MΩ); can be pulled above VDD. IOL = 1 mA at VOL ≤ 0.4 V (VDD ≥ 1.8 V)."+        "description": "Active-low, open-drain RESET output. Driven low when SENSE < VIT or MR is low, and remains asserted for the programmed reset delay (td) after both conditions clear. Requires an external pull-up (10 k\u03a9 to 1 M\u03a9); can be pulled above VDD. IOL = 1 mA at VOL \u2264 0.4 V (VDD \u2265 1.8 V)."       },       {         "number": "2",@@ -44,25 +47,25 @@         "number": "3",         "name": "MR",         "type": "input",-        "description": "Active-low manual reset input. Driving MR low asserts RESET. Internally pulled up to VDD by a 90 kΩ (typ, 70 kΩ min) resistor, so it may be left open if unused. VIL ≤ 0.3·VDD, VIH ≥ 0.7·VDD."+        "description": "Active-low manual reset input. Driving MR low asserts RESET. Internally pulled up to VDD by a 90 k\u03a9 (typ, 70 k\u03a9 min) resistor, so it may be left open if unused. VIL \u2264 0.3\u00b7VDD, VIH \u2265 0.7\u00b7VDD."       },       {         "number": "4",         "name": "CT",         "type": "input",-        "description": "Reset-period programming pin. Leaving CT open gives ~20 ms delay; tying CT to VDD via a 40 kΩ-200 kΩ resistor gives ~300 ms; connecting a ground-referenced capacitor (≥100 pF) gives user-programmable delay from 1.25 ms to 10 s."+        "description": "Reset-period programming pin. Leaving CT open gives ~20 ms delay; tying CT to VDD via a 40 k\u03a9-200 k\u03a9 resistor gives ~300 ms; connecting a ground-referenced capacitor (\u2265100 pF) gives user-programmable delay from 1.25 ms to 10 s."       },       {         "number": "5",         "name": "SENSE",         "type": "input",-        "description": "Analog voltage-sense input. Compared to internal threshold VIT (0.405 V for the G01 adjustable version). RESET is asserted when VSENSE drops below VIT. Input current typ ±1.7 nA (±25 nA max for G01). Absolute max 6.5 V."+        "description": "Analog voltage-sense input. Compared to internal threshold VIT (0.405 V for the G01 adjustable version). RESET is asserted when VSENSE drops below VIT. Input current typ \u00b11.7 nA (\u00b125 nA max for G01). Absolute max 6.5 V."       },       {         "number": "6",         "name": "VDD",         "type": "power_in",-        "description": "Supply voltage input, 1.7 V to 6.5 V operating range. TI recommends a 0.1 µF ceramic bypass capacitor close to the pin. Typical IDD = 2.4 µA at VDD = 3.3 V."+        "description": "Supply voltage input, 1.7 V to 6.5 V operating range. TI recommends a 0.1 \u00b5F ceramic bypass capacitor close to the pin. Typical IDD = 2.4 \u00b5A at VDD = 3.3 V."       }     ],     "provenance": {

@@ -60,6 +60,18 @@   <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="5" x="1.1375" y="-0.0000" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="6" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-1.4500" y="1.5100"/>+    <vertex x="-1.6900" y="1.8400"/>+    <vertex x="-1.2100" y="1.8400"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.4000" y="1.4500"/>+    <vertex x="0.8000" y="1.4500"/>+    <vertex x="0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="1.0500"/>+  </polygon>   <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@   <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/>   <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="TPS3808G01DBVR">@@ -102,7 +114,14 @@         <connect gate="G$1" pin="SENSE" pad="5"/>         <connect gate="G$1" pin="CT" pad="4"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="TPS3808G01DBVR" constant="no"/>+          <attribute name="MANUFACTURER" value="Texas Instruments" constant="no"/>+          <attribute name="DIGIKEY_PN" value="296-17188-2-ND" constant="no"/>+          <attribute name="LCSC_PN" value="C19653" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>