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TPS2350DR
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Texas Instruments Supervisor And Reset ICs, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# TPS2350DR++**Texas Instruments** · Supervisor And Reset ICs · SOIC-14++TPS2350DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RTN | power_in | Supply return (ground) and positive supply input; for negative voltage systems it connects directly to the return node of the input power bus. |+| 2 | FLT | output | Open-drain, active-low fault indication that sinks up to 10 mA when in fault, withstands 80 V without leakage when not faulted, and is pulled to the lower of -VINA and -VINB. |+| 3 | UV | input | Under-voltage comparator input, typically driven from a divider between RTN and SOURCE, that enables the linear current amplifier when UV is more than 1.4 V above SOURCE. |+| 4 | OV | input | Over-voltage comparator input, typically driven from a divider between RTN and SOURCE, that disables the linear current amplifier when OV is 1.4 V or more above SOURCE. |+| 5 | FLTTIM | bidirectional | Fault timer pin where an external capacitor from FLTTIM to SOURCE sets the fault timeout, charged to the 4-V fault threshold and discharged at about 1% of the charge rate to set the retry duty cycle. |+| 6 | RAMP | bidirectional | Inrush slew-rate programming pin where an external capacitor between RAMP and SOURCE sets the turn-on current slew rate; when fully charged RAMP can exceed SOURCE by 6 V while the reference is clamped to 42 mV. |+| 7 | SOURCE | bidirectional | Negative current sense input connected to the sources of the supply-selector FETs and the negative terminal of the current sense resistor, which connects SOURCE to the more negative of -VINA and -VINB. |+| 8 | GATB | output | Gate drive for the external N-channel FET that selects -VINB; it is pulled 14 V above -VINB when -VINB is more negative than -VINA and pulled down to -VINA otherwise. |+| 9 | GATA | output | Gate drive for the external N-channel FET that selects -VINA; it is pulled 14 V above -VINA when -VINA is more negative than -VINB and pulled down to -VINB otherwise. |+| 10 | SENSE | input | Positive current sense input, used with a low-value resistor to SOURCE, that the linear current amplifier regulates to 42 mV and that trips the 120-mV overload threshold on fast faults. |+| 11 | GAT | output | Gate drive for the external N-channel protection MOSFET that ramps load current and disconnects on a fault, driven 14 V above SOURCE when fully enhanced. |+| 12 | PG | output | Open-drain, active-high power-good output indicating the power FET is fully enhanced; it sinks up to 10 mA, withstands 80 V without leakage when power is not good, and is pulled to the lower of -VINA and -VINB. |+| 13 | -VINB | power_in | Negative supply input B, connected directly to the second input supply negative rail (recommended supply -12 V to -80 V with respect to RTN). |+| 14 | -VINA | power_in | Negative supply input A, connected directly to the first input supply negative rail (recommended supply -12 V to -80 V with respect to RTN). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Power Management (PMIC) |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `TPS2350DR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `tps2350dr-etched.step` / `tps2350dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps2350dr.step` / `tps2350dr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps2350.pdf) (30 pp, sha256 `99780b23bedb684a`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps2350dr-datasheet.pdf)
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for negative voltage systems it connects directly to the return node of the input power bus."+ },+ {+ "number": "2",+ "name": "FLT",+ "type": "output",+ "description": "Open-drain, active-low fault indication that sinks up to 10 mA when in fault, withstands 80 V without leakage when not faulted, and is pulled to the lower of -VINA and -VINB."+ },+ {+ "number": "3",+ "name": "UV",+ "type": "input",+ "description": "Under-voltage comparator input, typically driven from a divider between RTN and SOURCE, that enables the linear current amplifier when UV is more than 1.4 V above SOURCE."+ },+ {+ "number": "4",+ "name": "OV",+ "type": "input",+ "description": "Over-voltage comparator input, typically driven from a divider between RTN and SOURCE, that disables the linear current amplifier when OV is 1.4 V or more above SOURCE."+ },+ {+ "number": "5",+ "name": "FLTTIM",+ "type": "bidirectional",+ "description": "Fault timer pin where an external capacitor from FLTTIM to SOURCE sets the fault timeout, charged to the 4-V fault threshold and discharged at about 1% of the charge rate to set the retry duty cycle."+ },+ {+ "number": "6",+ "name": "RAMP",+ "type": "bidirectional",+ "description": "Inrush slew-rate programming pin where an external capacitor between RAMP and SOURCE sets the turn-on current slew rate; when fully charged RAMP can exceed SOURCE by 6 V while the reference is clamped to 42 mV."+ },+ {+ "number": "7",+ "name": "SOURCE",+ "type": "bidirectional",+ "description": "Negative current sense input connected to the sources of the supply-selector FETs and the negative terminal of the current sense resistor, which connects SOURCE to the more negative of -VINA and -VINB."+ },+ {+ "number": "8",+ "name": "GATB",+ "type": "output",+ "description": "Gate drive for the external N-channel FET that selects -VINB; it is pulled 14 V above -VINB when -VINB is more negative than -VINA and pulled down to -VINA otherwise."+ },+ {+ "number": "9",+ "name": "GATA",+ "type": "output",+ "description": "Gate drive for the external N-channel FET that selects -VINA; it is pulled 14 V above -VINA when -VINA is more negative than -VINB and pulled down to -VINB otherwise."+ },+ {+ "number": "10",+ "name": "SENSE",+ "type": "input",+ "description": "Positive current sense input, used with a low-value resistor to SOURCE, that the linear current amplifier regulates to 42 mV and that trips the 120-mV overload threshold on fast faults."+ },+ {+ "number": "11",+ "name": "GAT",+ "type": "output",+ "description": "Gate drive for the external N-channel protection MOSFET that ramps load current and disconnects on a fault, driven 14 V above SOURCE when fully enhanced."+ },+ {+ "number": "12",+ "name": "PG",+ "type": "output",+ "description": "Open-drain, active-high power-good output indicating the power FET is fully enhanced; it sinks up to 10 mA, withstands 80 V without leakage when power is not good, and is pulled to the lower of -VINA and -VINB."+ },+ {+ "number": "13",+ "name": "–VINB",+ "type": "power_in",+ "description": "Negative supply input B, connected directly to the second input supply negative rail (recommended supply -12 V to -80 V with respect to RTN)."+ },+ {+ "number": "14",+ "name": "–VINA",+ "type": "power_in",+ "description": "Negative supply input A, connected directly to the first input supply negative rail (recommended supply -12 V to -80 V with respect to RTN)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet pin table classifies RTN and –VINA/–VINB as 'I' (input), but they are supply pins; I u; Pin numbers were cross-checked between the top-view pin diagram (page 2) and the pin function table "+ ],+ "pages_sent": 9,+ "cost_usd": 0.0673,+ "at": "2026-10-08T16:11:44"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/tps2350.pdf",+ "pages": 30,+ "sha256": "99780b23bedb684a",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps2350dr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps2350dr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "01d86a666a7940de299c2a9d7bb84725f30fa2a433ee0440121c5fa13a072415",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}