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Initial commit: component/tph7r006pl

Ray ·dba7374460 ·1mo ago
2 files changed +77
README.mdadded+43
@@ -0,0 +1,43 @@+# TPH7R006PL++**TOSHIBA** · MOSFETs · SOP-8++TPH7R006PL from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | S | passive | Source terminal (leg 1). Ganged with pins 2 and 3 to a common source pad; carries drain current back to the low-side rail. Absolute max VGSS = ±20 V. |+| 2 | S | passive | Source terminal (leg 2). Ganged with pins 1 and 3. Sharing multiple leads reduces package and PCB source inductance for fast switching. |+| 3 | S | passive | Source terminal (leg 3). Ganged with pins 1 and 2 to the common source. Tie all three source pins together on the PCB. |+| 4 | G | input | Gate control input. Vth = 1.5 to 2.5 V (VDS = 10 V, ID = 0.2 mA); recommended drive VGS = 10 V; absolute max VGSS = ±20 V. Qg ≈ 22 nC typ. at VGS = 10 V, gate resistance rg ≈ 0.8 Ω typ. |+| 5 | D | passive | Drain terminal (leg 5). Ganged with pins 6, 7 and 8 to the common drain (and thermal) pad. VDSS = 60 V max. |+| 6 | D | passive | Drain terminal (leg 6). Ganged with pins 5, 7 and 8. Multiple drain pins carry the main switched current and conduct heat out through the SOP Advance drain pad. |+| 7 | D | passive | Drain terminal (leg 7). Ganged with pins 5, 6 and 8. Tie all four drain pins to the drain net/copper pour. |+| 8 | D | passive | Drain terminal (leg 8). Ganged with pins 5, 6 and 7 to the common drain. ID = 60 A continuous at Tc = 25 °C (silicon-limit 79 A). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | TOSHIBA |+| Package | SOP-8 |+| Category | Transistors/Thyristors |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `TPH7R006PL`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [TOSHIBA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904149586358272) (None pp, sha256 `ca2279558c4038f1`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tph7r006pl-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "tph7r006pl",+  "version": "0.1.0",+  "type": "component",+  "description": "TOSHIBA MOSFETs, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "transistors-thyristors",+    "tph7r006pl"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "tph7r006pl.kicad_sym",+    "tph7r006pl.kicad_mod",+    "tph7r006pl.glb",+    "tph7r006pl.step",+    "tph7r006pl.lbr",+    "docs/hero.png",+    "docs/tph7r006pl-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file