component
TPH7R006PL
Public Made by Adomby adom
TOSHIBA MOSFETs, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+117−8@@ -1,13 +1,127 @@ {+ "schema_version": 1,+ "type": "component", "slug": "tph7r006pl",+ "title": "TPH7R006PL",+ "brief": "TOSHIBA MOSFETs, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "TOSHIBA MOSFETs, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "transistors-thyristors", "tph7r006pl" ],+ "component": {+ "mpn": "TPH7R006PL",+ "manufacturer": "TOSHIBA",+ "package": "SOP-8",+ "pin_count": 8,+ "category": "Transistors/Thyristors",+ "subcategory": "MOSFETs",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904149586358272",+ "parts": {+ "symbol": "tph7r006pl.kicad_sym",+ "footprint": "tph7r006pl.kicad_mod",+ "model_3d": "tph7r006pl.glb",+ "model_3d_step": "tph7r006pl.step",+ "lbr": "tph7r006pl.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "S",+ "type": "passive",+ "description": "Source terminal (leg 1). Ganged with pins 2 and 3 to a common source pad; carries drain current back to the low-side rail. Absolute max VGSS = \u00b120 V."+ },+ {+ "number": "2",+ "name": "S",+ "type": "passive",+ "description": "Source terminal (leg 2). Ganged with pins 1 and 3. Sharing multiple leads reduces package and PCB source inductance for fast switching."+ },+ {+ "number": "3",+ "name": "S",+ "type": "passive",+ "description": "Source terminal (leg 3). Ganged with pins 1 and 2 to the common source. Tie all three source pins together on the PCB."+ },+ {+ "number": "4",+ "name": "G",+ "type": "input",+ "description": "Gate control input. Vth = 1.5 to 2.5 V (VDS = 10 V, ID = 0.2 mA); recommended drive VGS = 10 V; absolute max VGSS = \u00b120 V. Qg \u2248 22 nC typ. at VGS = 10 V, gate resistance rg \u2248 0.8 \u03a9 typ."+ },+ {+ "number": "5",+ "name": "D",+ "type": "passive",+ "description": "Drain terminal (leg 5). Ganged with pins 6, 7 and 8 to the common drain (and thermal) pad. VDSS = 60 V max."+ },+ {+ "number": "6",+ "name": "D",+ "type": "passive",+ "description": "Drain terminal (leg 6). Ganged with pins 5, 7 and 8. Multiple drain pins carry the main switched current and conduct heat out through the SOP Advance drain pad."+ },+ {+ "number": "7",+ "name": "D",+ "type": "passive",+ "description": "Drain terminal (leg 7). Ganged with pins 5, 6 and 8. Tie all four drain pins to the drain net/copper pour."+ },+ {+ "number": "8",+ "name": "D",+ "type": "passive",+ "description": "Drain terminal (leg 8). Ganged with pins 5, 6 and 7 to the common drain. ID = 60 A continuous at Tc = 25 \u00b0C (silicon-limit 79 A)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904149586358272",+ "pages": null,+ "sha256": "ca2279558c4038f1",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "TOSHIBA",+ "Package": "SOP-8",+ "Category": "Transistors/Thyristors",+ "Pins": "8"+ }+ },+ "variants": [],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "tph7r006pl"+ ],+ "discovery_pitch": "TPH7R006PL (TOSHIBA) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +139,5 @@ "docs/tph7r006pl-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }