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tp8485e-sr: factory component page (tier=lcsc)

Ray ·896fa509b7 ·1mo ago ·parent 390c5de
1 file changed +116−8
page.json+116−8
@@ -1,13 +1,126 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "tp8485e-sr",+  "title": "TP8485E-SR",+  "brief": "3PEAK RS-485 / RS-422 ICs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "3PEAK RS-485 / RS-422 ICs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "interface",     "tp8485e-sr"   ],+  "component": {+    "mpn": "TP8485E-SR",+    "manufacturer": "3PEAK",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "Interface",+    "subcategory": "RS-485 / RS-422 ICs",+    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/5028361a5ce54ad5bc5b997e6139f019.pdf",+    "parts": {+      "symbol": "tp8485e-sr.kicad_sym",+      "footprint": "tp8485e-sr.kicad_mod",+      "model_3d": "tp8485e-sr.glb",+      "model_3d_step": "tp8485e-sr.step",+      "lbr": "tp8485e-sr.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "R",+        "type": "output",+        "description": "Receiver output. CMOS logic level output derived from the differential bus (A/Y \u2212 B/Z). High-Z when the receiver is disabled (/RE = high or open). VOH \u2265 4.64 V and VOL \u2264 0.27 V at \u00b18 mA drive with VCC = 5 V."+      },+      {+        "number": "2",+        "name": "/RE",+        "type": "input",+        "description": "Receiver enable, active low. Drive low to enable the receiver output R; drive high or leave open to place R in high-impedance. CMOS input, typical input current 10 nA."+      },+      {+        "number": "3",+        "name": "DE",+        "type": "input",+        "description": "Driver enable, active high. Drive high to enable the differential driver outputs A/Y and B/Z; drive low or leave open to place the driver outputs in high-impedance. CMOS input, typical input current 10 nA."+      },+      {+        "number": "4",+        "name": "D",+        "type": "input",+        "description": "Driver data input. CMOS logic level input; when the driver is enabled, D=H drives A/Y high and B/Z low, D=L drives the opposite. Left open the driver behaves as if D=H (actively drives bus high). Referenced to VCC/GND."+      },+      {+        "number": "5",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return for the device. Connect to the system ground plane; also serves as the reference for the bus common-mode voltage range of -8 V to +13 V."+      },+      {+        "number": "6",+        "name": "A/Y",+        "type": "bidirectional",+        "description": "Non-inverting RS-485 bus pin. Acts as receiver input A when the driver is disabled and as driver output Y when the driver is enabled. Withstands -15 V to +15 V DC and \u00b118 kV IEC61000-4-2 air-gap ESD; common-mode range -8 V to +13 V."+      },+      {+        "number": "7",+        "name": "B/Z",+        "type": "bidirectional",+        "description": "Inverting RS-485 bus pin. Acts as receiver input B when the driver is disabled and as driver output Z when the driver is enabled. Same absolute ratings as A/Y: -15 V to +15 V DC, \u00b118 kV IEC61000-4-2 air-gap ESD, common-mode -8 V to +13 V."+      },+      {+        "number": "8",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply, 3.0 V to 5.5 V recommended (absolute max 7 V). Bypass locally with a 100 nF ceramic capacitor to GND. Quiescent supply current is typically 695 \u00b5A with both driver and receiver enabled and no load."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://datasheet.lcsc.com/datasheet/pdf/5028361a5ce54ad5bc5b997e6139f019.pdf",+        "pages": 15,+        "sha256": "f7225ec86054a77b",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "3PEAK",+      "Package": "SOIC-8",+      "Category": "Interface",+      "Pins": "8"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "tp8485e-sr"+  ],+  "discovery_pitch": "TP8485E-SR (3PEAK) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +138,5 @@     "docs/tp8485e-sr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file