component
TP181C50S5
Public Made by Adomby adom
TECH PUBLIC Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C2827538). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+26−6
page.json+6−4@@ -26,13 +26,15 @@ "model_3d_step": "tp181c50s5.step", "lbr": "tp181c50s5.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C2827538"+ }, "pins": [ { "number": "1", "name": "VIN", "type": "power_in",- "description": "Power supply input. Absolute maximum -0.3 to +20 V; recommended operating range up to 18 V. Bypass with a 1 µF (1-10 µF) ceramic capacitor to GND close to the pin."+ "description": "Power supply input. Absolute maximum -0.3 to +20 V; recommended operating range up to 18 V. Bypass with a 1 \u00b5F (1-10 \u00b5F) ceramic capacitor to GND close to the pin." }, { "number": "2",@@ -44,7 +46,7 @@ "number": "3", "name": "CE", "type": "input",- "description": "Chip enable input. VCEH >= 1.3 V enables the regulator; VCEL <= 0.7 V disables it and engages the internal ~500 Ω output auto-discharge path. Absolute maximum GND-0.3 V to VIN+0.3 V. Do not leave floating."+ "description": "Chip enable input. VCEH >= 1.3 V enables the regulator; VCEL <= 0.7 V disables it and engages the internal ~500 \u03a9 output auto-discharge path. Absolute maximum GND-0.3 V to VIN+0.3 V. Do not leave floating." }, { "number": "4",@@ -56,7 +58,7 @@ "number": "5", "name": "VOUT", "type": "power_out",- "description": "Regulated 5.0 V output (4.9 V min / 5.1 V max at VIN=6.0 V, IOUT=30 mA). Delivers up to 300 mA with 120 mV typical dropout at 100 mA. Bypass with a 1 µF (1-10 µF) ceramic capacitor to GND; X5R/X7R recommended."+ "description": "Regulated 5.0 V output (4.9 V min / 5.1 V max at VIN=6.0 V, IOUT=30 mA). Delivers up to 300 mA with 120 mV typical dropout at 100 mA. Bypass with a 1 \u00b5F (1-10 \u00b5F) ceramic capacitor to GND; X5R/X7R recommended." } ], "provenance": {
tp181c50s5.lbr+20−2@@ -59,6 +59,18 @@ <smd name="3" x="-1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/> <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/> <smd name="5" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-1.4500" y="1.5100"/>+ <vertex x="-1.6900" y="1.8400"/>+ <vertex x="-1.2100" y="1.8400"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.4000" y="1.4500"/>+ <vertex x="0.8000" y="1.4500"/>+ <vertex x="0.8000" y="-1.4500"/>+ <vertex x="-0.8000" y="-1.4500"/>+ <vertex x="-0.8000" y="1.0500"/>+ </polygon> <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@ <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/> <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="TP181C50S5">@@ -100,7 +112,13 @@ <connect gate="G$1" pin="VOUT" pad="5"/> <connect gate="G$1" pin="NC" pad="4"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="TP181C50S5" constant="no"/>+ <attribute name="MANUFACTURER" value="TECH PUBLIC" constant="no"/>+ <attribute name="LCSC_PN" value="C2827538" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>