component
TNPW060378K7BEEA
Public Made by Adomby adom
Vishay Intertech Chip Resistor - Surface Mount, 0603. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Show the shared chip-thumbnailer cache widget and reusable artwork manifest
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+26−9
README.md+17−8@@ -1,20 +1,20 @@ # TNPW060378K7BEEA -Vishay TNPW e3 **78.7k ohm, ±0.1%, ±25 ppm/K**, nonpolar 0603 thin-film resistor. Candidate feedback component for [TMF8829 Depth Lab](https://wiki.adom.inc/adom/tmf8829-depth-lab). This is a component library in validation, not a qualified board or fabrication release.+Vishay TNPW e3 **78.7k ohm, ñ0.1%, ñ25 ppm/K**, nonpolar 0603 thin-film resistor. Candidate feedback component for [TMF8829 Depth Lab](https://wiki.adom.inc/adom/tmf8829-depth-lab). This is a component library in validation, not a qualified board or fabrication release. ## Manufacturer originals -- [TNPW e3 datasheet](https://www.vishay.com/docs/28758/tnpw_e3.pdf), revision 10-Apr-2026: ordering codes on page 4, dimensions on page 15. B means ±0.1%, E means ±25 ppm/K, EA means lead-free 5000-piece reel packaging. Distributor cut-tape terms need confirmation before procurement.+- [TNPW e3 datasheet](https://www.vishay.com/docs/28758/tnpw_e3.pdf), revision 10-Apr-2026: ordering codes on page 4, dimensions on page 15. B means ñ0.1%, E means ñ25 ppm/K, EA means lead-free 5000-piece reel packaging. Distributor cut-tape terms need confirmation before procurement. - [Original STEP archive](https://www.vishay.com/docs/28967/tnpw_e3_3dmodels.zip), linked directly by that datasheet: member `TNPW_V_e3/TNPW_e3_0603.stp`. Unchanged manufacturer bytes are preserved. The shared family geometry applies to this 0603 variant.-- [Recommended lands](https://www.vishay.com/docs/28950/recsoldpaddims-drabeyresfus.pdf), revision 12-Jul-2022. Selected IPC reflow recommendation: pads 0.90 à 1.00 mm, centers X ±0.80 mm, inner gap 0.70 mm, outer span 2.50 mm. Factory profile validation remains open.+- [Recommended lands](https://www.vishay.com/docs/28950/recsoldpaddims-drabeyresfus.pdf), revision 12-Jul-2022. Selected IPC reflow recommendation: pads 0.90 à1.00 mm, centers X ñ0.80 mm, inner gap 0.70 mm, outer span 2.50 mm. Factory profile validation remains open. ## Library construction and pose -The symbol derives from KiCad Device:R_US, obtained through service-kicad (KiCad libraries CC-BY-SA 4.0 with the library exception). Exact MPN/value, footprint and manufacturer datasheet fields are added. Both pins are passive: 1âpad 1, 2âpad 2. The part is nonpolar; the silk dot is an assembly pad-1 cue.+The symbol derives from KiCad Device:R_US, obtained through service-kicad (KiCad libraries CC-BY-SA 4.0 with the library exception). Exact MPN/value, footprint and manufacturer datasheet fields are added. Both pins are passive: 1âÂÂpad 1, 2âÂÂpad 2. The part is nonpolar; the silk dot is an assembly pad-1 cue. -The footprint was authored with adom-footprint from the manufacturer's land dimensions. Its generated full silk rectangle crossed the pads, so the project derivative replaces it with top/bottom lines clear of copper. Original generator output is retained locally. The fab outline is 1.55 à 0.85 mm; the courtyard encloses the pads with 0.25 mm clearance.+The footprint was authored with adom-footprint from the manufacturer's land dimensions. Its generated full silk rectangle crossed the pads, so the project derivative replaces it with top/bottom lines clear of copper. Original generator output is retained locally. The fab outline is 1.55 à0.85 mm; the courtyard encloses the pads with 0.25 mm clearance. -OCCT read-back of the manufacturer STEP is X 0..0.85, Y 0..1.55, Z 0..0.45 mm. The canonical candidate pose rotates Z â90° then translates (â0.775,+0.425,0) mm to center the body along the footprint X axis with floor Z=0. Actual contact seating in native KiCad/Fusion/Altium is still pending. The GLB is an OCCT visualization derivative; it does not replace the original STEP. Virtual MPN marking remains to be added as a separate annotation derivative.+OCCT read-back of the manufacturer STEP is X 0..0.85, Y 0..1.55, Z 0..0.45 mm. The canonical candidate pose rotates Z âÂÂ90ð then translates (âÂÂ0.775,+0.425,0) mm to center the body along the footprint X axis with floor Z=0. Actual contact seating in native KiCad/Fusion/Altium is still pending. The GLB is an OCCT visualization derivative; it does not replace the original STEP. Virtual MPN marking remains to be added as a separate annotation derivative. The adom-lbr JSON is canonical. KiCad exports are in `canonical-export/`, Fusion's complete deviceset is `TNPW060378K7BEEA.lbr`, and Altium libraries are in `exports/altium/`. Export success is not native application parity. @@ -27,13 +27,22 @@ These precision parts are a documented exception to the Basic Parts preference: ## 3D reference artwork -The derived display retains the source model geometry and materials, with a recorded rigid pose into Adom Z-up footprint coordinates. Nonphysical reference layers show teal dashed copper-pad boundaries at 50% opacity, silkscreen at 30% opacity, and signal names at 50% opacity. Labels follow the canonical pin-to-pad mapping. Unnamed nonpolarized passive connections are labeled âTerminalâ; no polarity or signal function is invented. Original manufacturer STEP files remain unchanged.+The derived display retains the source model geometry and materials, with a recorded rigid pose into Adom Z-up footprint coordinates. Nonphysical reference layers show teal dashed copper-pad boundaries at 50% opacity, silkscreen at 30% opacity, and signal names at 50% opacity. Labels follow the canonical pin-to-pad mapping. Unnamed nonpolarized passive connections are labeled âÂÂTerminalâÂÂ; no polarity or signal function is invented. Original manufacturer STEP files remain unchanged. Orbit underneath to compare contacts with copper boundaries. These are copper perimeters, not mask or paste apertures. Display artwork does not qualify native model seating, pin 1, electrical behavior or manufacture. The virtual MPN is applied through Adom Chip Laser at the chosen clear package surface described below. See `TNPW060378K7BEEA.adom-reference-v3.overlay.json` for source hashes, pose and layer metadata. ## MPN marking, source and license -**Mark location:** Center of resistor top, text width limited to 45 percent of package length to stay off metal terminations. The exact MPN is a virtual identification inlay generated by `adom-chip-laser`, not a claim about the manufacturer’s actual package marking. The physical source model and reference-artwork geometry remain unchanged.+**Mark location:** Center of resistor top, text width limited to 45 percent of package length to stay off metal terminations. The exact MPN is a virtual identification inlay generated by `adom-chip-laser`, not a claim about the manufacturerâs actual package marking. The physical source model and reference-artwork geometry remain unchanged. The Source field links to the manufacturer/reference authority. Generation tools such as adom-lbr, adom-symbol, step2glb and Adom Chip Laser are recorded separately in artifact provenance. Original Adom-authored content defaults to the MIT open-source license; manufacturer and upstream assets retain their original terms and attribution. See [license scope](LICENSE-Adom.md). Native CAD parity and manufacturing qualification are separate checks.+++## Cached chip artwork++These reusable chip previews and symbol outlines retain the reviewed Z-up pose and virtual MPN placement. Read the manifest before generating new artwork; compare its source hashes before reuse. Electrical and native model-seating qualification remain separate.++::adom-chip-thumbnail{src="/adom/tnpw060378k7beea/render/artwork/TNPW060378K7BEEA-thumbs.json"}++[Cache manifest and generation recipe](artwork/TNPW060378K7BEEA-thumbs.json) · [Original manufacturer STEP](TNPW_e3_0603.stp)
page.json+9−1@@ -44,5 +44,13 @@ "provenance": "generated" } },- "license": "MIT"+ "license": "MIT",+ "metadata": {+ "chip_thumbnail_cache": {+ "manifest": "artwork/TNPW060378K7BEEA-thumbs.json",+ "schema": "adom/chip-artwork-cache@1",+ "widget": "adom-chip-thumbnail",+ "reuse": "Verify source hashes and reuse the reviewed Z-up pose and surface-selected MPN placement."+ }+ } }