component
TMS320F28066PZT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+137@@ -0,0 +1,137 @@+# TMS320F28066PZT++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)++TMS320F28066PZT from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO42 | bidirectional | General-purpose I/O 42 (tri-state, internal pullup enabled at reset for non-PWM GPIO) with alternates EPWM8A output, TZ1 trip-zone input and COMP1OUT comparator 1 direct output; this pin exists only on the 100-pin PZ/PZP packages. |+| 2 | GPIO23/EQEP1I/MFSXA/SCIRXDB | bidirectional | General-purpose I/O 23 (tri-state) with alternates EQEP1 index, McBSP-A transmit frame sync and SCI-B receive data. |+| 3 | VDD | power_in | CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. |+| 4 | VSS | power_in | Digital ground pin. |+| 5 | VDDIO | power_in | Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin. |+| 6 | GPIO20/EQEP1A/MDXA/COMP1OUT | bidirectional | General-purpose I/O 20 (tri-state) with alternates EQEP1 input A, McBSP-A transmit serial data and COMP1OUT comparator 1 direct output. |+| 7 | GPIO21/EQEP1B/MDRA/COMP2OUT | bidirectional | General-purpose I/O 21 (tri-state) with alternates EQEP1 input B, McBSP-A receive serial data and COMP2OUT comparator 2 direct output. |+| 8 | GPIO43 | bidirectional | General-purpose I/O 43 (tri-state) with alternates EPWM8B output, TZ2 trip-zone input and COMP2OUT comparator 2 direct output; PZ/PZP only. |+| 9 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 (tri-state) with alternate function EPWM3A output and HRPWM channel (PWM pin pullup not enabled at reset). |+| 10 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | General-purpose I/O 5 (tri-state) with alternates EPWM3B output, SPI-A slave-in/master-out and ECAP1 capture I/O. |+| 11 | XRS | bidirectional | Device reset input and watchdog reset output, open-drain with internal pullup; a 2.2 kΩ to 10 kΩ resistor to VDDIO is recommended and any noise-filter capacitor to VSS should be 100 nF or smaller. |+| 12 | TRST | input | JTAG test reset with internal pulldown; must be held low during normal operation and an external pulldown (2.2 kΩ generally adequate) is required. |+| 13 | VDDIO | power_in | Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin. |+| 14 | VDD | power_in | CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. |+| 15 | VSS | power_in | Digital ground pin. |+| 16 | ADCINA7 | input | ADC Group A, channel 7 analog input. |+| 17 | ADCINA6/COMP3A/AIO6 | input | ADC Group A, channel 6 analog input, also comparator 3A input and digital AIO6 (AIO pins have no internal pullup). |+| 18 | ADCINA5 | input | ADC Group A, channel 5 analog input. |+| 19 | ADCINA4/COMP2A/AIO4 | input | ADC Group A, channel 4 analog input, also comparator 2A input and digital AIO4. |+| 20 | ADCINA3 | input | ADC Group A, channel 3 analog input. |+| 21 | ADCINA2/COMP1A/AIO2 | input | ADC Group A, channel 2 analog input, also comparator 1A input and digital AIO2. |+| 22 | ADCINA1 | input | ADC Group A, channel 1 analog input. |+| 23 | ADCINA0 | input | ADC Group A, channel 0 analog input; on the PZ package it is separate from VREFHI. |+| 24 | VREFHI | power_in | ADC external reference high, used only in ADC external reference mode; VREFHI must not exceed VDDA. |+| 25 | VDDA | power_in | Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin. |+| 26 | VSSA | power_in | Analog ground pin. |+| 27 | VREFLO | power_in | ADC external reference low. |+| 28 | ADCINB0 | input | ADC Group B, channel 0 analog input. |+| 29 | ADCINB1 | input | ADC Group B, channel 1 analog input. |+| 30 | ADCINB2/COMP1B/AIO10 | input | ADC Group B, channel 2 analog input, also comparator 1B input and digital AIO10. |+| 31 | ADCINB3 | input | ADC Group B, channel 3 analog input. |+| 32 | ADCINB4/COMP2B/AIO12 | input | ADC Group B, channel 4 analog input, also comparator 2B input and digital AIO12. |+| 33 | ADCINB5 | input | ADC Group B, channel 5 analog input. |+| 34 | ADCINB6/COMP3B/AIO14 | input | ADC Group B, channel 6 analog input, also comparator 3B input and digital AIO14. |+| 35 | ADCINB7 | input | ADC Group B, channel 7 analog input. |+| 36 | VSS | power_in | Digital ground pin. |+| 37 | VDD | power_in | CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. |+| 38 | VDDIO | power_in | Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin. |+| 39 | GPIO25/ECAP2/EQEP2B/SPISOMIB | bidirectional | General-purpose I/O 25 (tri-state) with alternates ECAP2, EQEP2 input B (PZ/PZP only) and SPI-B slave-out/master-in. |+| 40 | GPIO31/CANTXA/EQEP2S/EPWM8A | bidirectional | General-purpose I/O 31 (tri-state) with alternates eCAN-A transmit, EQEP2 strobe (PZ/PZP only) and EPWM8A output. |+| 41 | GPIO30/CANRXA/EQEP2I/EPWM7A | bidirectional | General-purpose I/O 30 (tri-state) with alternates eCAN-A receive, EQEP2 index (PZ/PZP only) and EPWM7A output. |+| 42 | GPIO50/EQEP1A/MDXA/TZ1 | bidirectional | General-purpose I/O 50 (tri-state) with alternates EQEP1 input A, McBSP-A transmit data and TZ1 trip-zone input; PZ/PZP only. |+| 43 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 (tri-state) with alternates SCI-A transmit data, I2C clock open-drain (SCLA) and TZ3 trip-zone input. |+| 44 | GPIO12 | bidirectional | General-purpose I/O 12 (tri-state) with alternates TZ1 trip-zone input, SCI-A transmit data and SPI-B slave-in/master-out. |+| 45 | TEST2 | bidirectional | Reserved for TI test use; must be left unconnected. |+| 46 | VDD3VFL | power_in | 3.3-V flash core power pin; this pin should be connected to 3.3 V at all times. |+| 47 | VSS | power_in | Digital ground pin. |+| 48 | GPIO51/EQEP1B/MDRA/TZ2 | bidirectional | General-purpose I/O 51 (tri-state) with alternates EQEP1 input B, McBSP-A receive data and TZ2 trip-zone input; PZ/PZP only. |+| 49 | GPIO9/EPWM5B/SCITXDB/ECAP3 | bidirectional | General-purpose I/O 9 (tri-state) with alternates EPWM5B output, SCI-B transmit data and ECAP3 capture I/O. |+| 50 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 (tri-state) with alternates SCI-A receive data, I2C data open-drain (SDAA) and TZ2 trip-zone input. |+| 51 | GPIO18/SPICLKA/SCITXDB/XCLKOUT | bidirectional | General-purpose I/O 18 (tri-state) with alternates SPI-A clock, SCI-B transmit data and XCLKOUT (SYSCLKOUT/4 at reset); XCLKOUT requires the GPIO18 mux set to XCLKOUT. |+| 52 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 (tri-state) with alternates SPI-A slave-out/master-in and TZ3 trip-zone input. |+| 53 | GPIO52/EQEP1S/MCLKXA/TZ3 | bidirectional | General-purpose I/O 52 (tri-state) with alternates EQEP1 strobe, McBSP-A transmit clock and TZ3 trip-zone input; PZ/PZP only. |+| 54 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | General-purpose I/O 8 (tri-state) with alternates EPWM5A output and HRPWM channel and ADC start-of-conversion A output. |+| 55 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 (tri-state) with alternates SPI-A slave-in/master-out and TZ2 trip-zone input. |+| 56 | GPIO44/MFSRA/SCIRXDB/EPWM7B | bidirectional | General-purpose I/O 44 (tri-state) with alternates McBSP-A receive frame sync, SCI-B receive data and EPWM7B output; PZ/PZP only. |+| 57 | GPIO7/EPWM4B/SCIRXDA/ECAP2 | bidirectional | General-purpose I/O 7 (tri-state) with alternates EPWM4B output, SCI-A receive data and ECAP2 capture I/O. |+| 58 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 (tri-state) with alternates EPWM4A output and HRPWM channel, ePWM sync input and ePWM sync output. |+| 59 | X2 | output | On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 must be left unconnected if not used. |+| 60 | X1 | input | On-chip 1.8-V crystal oscillator input; a quartz crystal or ceramic resonator is connected across X1 and X2, and the pin must be tied to GND if not used. |+| 61 | VDDIO | power_in | Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin. |+| 62 | VSS | power_in | Digital ground pin. |+| 63 | VDD | power_in | CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. |+| 64 | GPIO19 | bidirectional | General-purpose I/O 19 (tri-state) with alternates external oscillator input XCLKIN (path not gated by the mux), SPI-A slave transmit enable, SCI-B receive data and ECAP1; glitches during VREG power-up. |+| 65 | GPIO53/EQEP1I/MFSXA | bidirectional | General-purpose I/O 53 (tri-state) with alternates EQEP1 index and McBSP-A transmit frame sync; PZ/PZP only. |+| 66 | GPIO39 | bidirectional | General-purpose I/O 39 (tri-state) with no peripheral alternate function listed for this pin. |+| 67 | GPIO38/XCLKIN/TCK | bidirectional | General-purpose I/O 38 (tri-state) with alternates XCLKIN external oscillator input and JTAG TCK (internal pullup); TCK function is active during JTAG debug. |+| 68 | GPIO34/COMP2OUT/COMP3OUT | bidirectional | General-purpose I/O 34 (tri-state) with alternates COMP2OUT and COMP3OUT comparator direct outputs; not glitch-free during power-up when VREG is used. |+| 69 | GPIO54/SPISIMOA/EQEP2A/HRCAP1 | bidirectional | General-purpose I/O 54 (tri-state) with alternates SPI-A slave-in/master-out, EQEP2 input A and HRCAP1 high-resolution capture input; PZ/PZP only. |+| 70 | GPIO37/TDO | tri_state | General-purpose I/O 37 with JTAG scan data output TDO, shifted out on the falling edge of TCK with 8-mA drive. |+| 71 | GPIO35/TDI | bidirectional | General-purpose I/O 35 with JTAG test data input TDI, which has an internal pullup and is clocked on the rising edge of TCK. |+| 72 | GPIO36/TMS | bidirectional | General-purpose I/O 36 with JTAG test-mode select TMS, which has an internal pullup and is clocked on the rising edge of TCK. |+| 73 | GPIO11/EPWM6B/SCIRXDB/ECAP1 | bidirectional | General-purpose I/O 11 (tri-state) with alternates EPWM6B output, SCI-B receive data and ECAP1 capture I/O. |+| 74 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | General-purpose I/O 10 (tri-state) with alternates EPWM6A output and HRPWM channel and ADC start-of-conversion B output. |+| 75 | GPIO55/SPISOMIA/EQEP2B/HRCAP2 | bidirectional | General-purpose I/O 55 (tri-state) with alternates SPI-A slave-out/master-in, EQEP2 input B and HRCAP2 capture input; PZ/PZP only. |+| 76 | GPIO41/EPWM7B/SCIRXDB | bidirectional | General-purpose I/O 41 (tri-state) with alternates EPWM7B output and SCI-B receive data; PZ/PZP only. |+| 77 | GPIO27/HRCAP2/EQEP2S/SPISTEB/USB0DM | bidirectional | General-purpose I/O 27 (tri-state) with alternates HRCAP2, EQEP2 strobe, SPI-B slave transmit enable and USB0DM negative differential signal (enabled via USBIOEN in GPACTRL2). |+| 78 | GPIO26/ECAP3/EQEP2I/SPICLKB/USB0DP | bidirectional | General-purpose I/O 26 (tri-state) with alternates ECAP3, EQEP2 index, SPI-B clock and USB0DP positive differential signal (enabled via USBIOEN in GPACTRL2); glitches during VREG power-up. |+| 79 | VDDIO | power_in | Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin. |+| 80 | VSS | power_in | Digital ground pin. |+| 81 | VDD | power_in | CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. |+| 82 | GPIO40/EPWM7A/SCITXDB | bidirectional | General-purpose I/O 40 (tri-state) with alternates EPWM7A output and SCI-B transmit data; PZ/PZP only. |+| 83 | GPIO3/EPWM2B/SPISOMIA/COMP2OUT | bidirectional | General-purpose I/O 3 (tri-state) with alternates EPWM2B output, SPI-A slave-out/master-in and COMP2OUT comparator 2 direct output. |+| 84 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 (tri-state) with alternate function EPWM2A output and HRPWM channel. |+| 85 | GPIO56/SPICLKA/EQEP2I/HRCAP3 | bidirectional | General-purpose I/O 56 (tri-state) with alternates SPI-A clock, EQEP2 index and HRCAP3 capture input; PZ/PZP only. |+| 86 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 (tri-state) with alternates EPWM1B output and COMP1OUT comparator 1 direct output. |+| 87 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 (tri-state) with alternate function EPWM1A output and HRPWM channel. |+| 88 | GPIO15/ECAP2/SCIRXDB/SPISTEB | bidirectional | General-purpose I/O 15 (tri-state) with alternates ECAP2 capture I/O, SCI-B receive data and SPI-B slave transmit enable. |+| 89 | GPIO57 | bidirectional | General-purpose I/O 57 (tri-state) with alternates SPI-A slave transmit enable, EQEP2 strobe and HRCAP4 capture input; PZ/PZP only. |+| 90 | VREGENZ | input | Internal voltage regulator enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or to VDDIO to disable it and use an external 1.8-V supply. |+| 91 | VDD | power_in | CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. |+| 92 | VSS | power_in | Digital ground pin. |+| 93 | VDDIO | power_in | Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin. |+| 94 | GPIO58/MCLKRA/SCITXDB/EPWM7A | bidirectional | General-purpose I/O 58 (tri-state) with alternates McBSP-A receive clock, SCI-B transmit data and EPWM7A output; PZ/PZP only. |+| 95 | GPIO13 | bidirectional | General-purpose I/O 13 (tri-state) with alternates TZ2 trip-zone input and SPI-B slave-out/master-in. |+| 96 | GPIO14 | bidirectional | General-purpose I/O 14 (tri-state) with alternates TZ3 trip-zone input, SCI-B transmit data and SPI-B clock. |+| 97 | GPIO24/ECAP1/EQEP2A/SPISIMOB | bidirectional | General-purpose I/O 24 (tri-state) with alternates ECAP1, EQEP2 input A (PZ/PZP only) and SPI-B slave-in/master-out. |+| 98 | GPIO22/EQEP1S/MCLKXA/SCITXDB | bidirectional | General-purpose I/O 22 (tri-state) with alternates EQEP1 strobe, McBSP-A transmit clock and SCI-B transmit data. |+| 99 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 (tri-state) with alternates I2C data open-drain (SDAA), ePWM sync input and ADC start-of-conversion A output. |+| 100 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 (tri-state) with alternates I2C clock open-drain (SCLA), ePWM sync output and ADC start-of-conversion B output. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-100(14x14) |+| Category | Embedded Processors & Controllers |+| Pins | 100 |++## CAD (KiCad official)++- Symbol: `TMS320F28066PZT`+- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`+- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)+- 3D model files: `tms320f28066pzt-etched.step` / `tms320f28066pzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28066pzt.step` / `tms320f28066pzt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28062f) (206 pp, sha256 `3033efed856fc72a`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320f28066pzt-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320f28066pzt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320f28066pzt.kicad_sym",+ "tms320f28066pzt.kicad_mod",+ "tms320f28066pzt.glb",+ "tms320f28066pzt.step",+ "tms320f28066pzt.lbr",+ "docs/hero.png",+ "docs/tms320f28066pzt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tms320f28066pzt-hero.glb",+ "tms320f28066pzt-hero.overlay.json"+ ],+ "component": {+ "mpn": "TMS320F28066PZT",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-100(14x14)",+ "pin_count": 100,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f28062f",+ "parts": {+ "symbol": "tms320f28066pzt.kicad_sym",+ "footprint": "tms320f28066pzt.kicad_mod",+ "model_3d": "tms320f28066pzt-hero.glb",+ "model_3d_plain": "tms320f28066pzt.glb",+ "model_3d_step": "tms320f28066pzt-etched.step",+ "model_3d_step_plain": "tms320f28066pzt.step",+ "lbr": "tms320f28066pzt.lbr"+ },+ "distributor_links": {+ "lcsc": "C1337902",+ "digikey": "296-46497-ND",+ "mouser": "595-TMS320F28066PZT"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T02:02:18Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-46497-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TMS320F28066PZT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO42",+ "type": "bidirectional",+ "description": "General-purpose I/O 42 (tri-state, internal pullup enabled at reset for non-PWM GPIO) with alternates EPWM8A output, TZ1 trip-zone input and COMP1OUT comparator 1 direct output; this pin exists only on the 100-pin PZ/PZP packages."+ },+ {+ "number": "2",+ "name": "GPIO23/EQEP1I/MFSXA/SCIRXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 23 (tri-state) with alternates EQEP1 index, McBSP-A transmit frame sync and SCI-B receive data."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground."+ },+ {+ "number": "4",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "5",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin."+ },+ {+ "number": "6",+ "name": "GPIO20/EQEP1A/MDXA/COMP1OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 20 (tri-state) with alternates EQEP1 input A, McBSP-A transmit serial data and COMP1OUT comparator 1 direct output."+ },+ {+ "number": "7",+ "name": "GPIO21/EQEP1B/MDRA/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 21 (tri-state) with alternates EQEP1 input B, McBSP-A receive serial data and COMP2OUT comparator 2 direct output."+ },+ {+ "number": "8",+ "name": "GPIO43",+ "type": "bidirectional",+ "description": "General-purpose I/O 43 (tri-state) with alternates EPWM8B output, TZ2 trip-zone input and COMP2OUT comparator 2 direct output; PZ/PZP only."+ },+ {+ "number": "9",+ "name": "GPIO4/EPWM3A",+ "type": "bidirectional",+ "description": "General-purpose I/O 4 (tri-state) with alternate function EPWM3A output and HRPWM channel (PWM pin pullup not enabled at reset)."+ },+ {+ "number": "10",+ "name": "GPIO5/EPWM3B/SPISIMOA/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 5 (tri-state) with alternates EPWM3B output, SPI-A slave-in/master-out and ECAP1 capture I/O."+ },+ {+ "number": "11",+ "name": "XRS",+ "type": "bidirectional",+ "description": "Device reset input and watchdog reset output, open-drain with internal pullup; a 2.2 kΩ to 10 kΩ resistor to VDDIO is recommended and any noise-filter capacitor to VSS should be 100 nF or smaller."+ },+ {+ "number": "12",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset with internal pulldown; must be held low during normal operation and an external pulldown (2.2 kΩ generally adequate) is required."+ },+ {+ "number": "13",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground."+ },+ {+ "number": "15",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "16",+ "name": "ADCINA7",+ "type": "input",+ "description": "ADC Group A, channel 7 analog input."+ },+ {+ "number": "17",+ "name": "ADCINA6/COMP3A/AIO6",+ "type": "input",+ "description": "ADC Group A, channel 6 analog input, also comparator 3A input and digital AIO6 (AIO pins have no internal pullup)."+ },+ {+ "number": "18",+ "name": "ADCINA5",+ "type": "input",+ "description": "ADC Group A, channel 5 analog input."+ },+ {+ "number": "19",+ "name": "ADCINA4/COMP2A/AIO4",+ "type": "input",+ "description": "ADC Group A, channel 4 analog input, also comparator 2A input and digital AIO4."+ },+ {+ "number": "20",+ "name": "ADCINA3",+ "type": "input",+ "description": "ADC Group A, channel 3 analog input."+ },+ {+ "number": "21",+ "name": "ADCINA2/COMP1A/AIO2",+ "type": "input",+ "description": "ADC Group A, channel 2 analog input, also comparator 1A input and digital AIO2."+ },+ {+ "number": "22",+ "name": "ADCINA1",+ "type": "input",+ "description": "ADC Group A, channel 1 analog input."+ },+ {+ "number": "23",+ "name": "ADCINA0",+ "type": "input",+ "description": "ADC Group A, channel 0 analog input; on the PZ package it is separate from VREFHI."+ },+ {+ "number": "24",+ "name": "VREFHI",+ "type": "power_in",+ "description": "ADC external reference high, used only in ADC external reference mode; VREFHI must not exceed VDDA."+ },+ {+ "number": "25",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin."+ },+ {+ "number": "26",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground pin."+ },+ {+ "number": "27",+ "name": "VREFLO",+ "type": "power_in",+ "description": "ADC external reference low."+ },+ {+ "number": "28",+ "name": "ADCINB0",+ "type": "input",+ "description": "ADC Group B, channel 0 analog input."+ },+ {+ "number": "29",+ "name": "ADCINB1",+ "type": "input",+ "description": "ADC Group B, channel 1 analog input."+ },+ {+ "number": "30",+ "name": "ADCINB2/COMP1B/AIO10",+ "type": "input",+ "description": "ADC Group B, channel 2 analog input, also comparator 1B input and digital AIO10."+ },+ {+ "number": "31",+ "name": "ADCINB3",+ "type": "input",+ "description": "ADC Group B, channel 3 analog input."+ },+ {+ "number": "32",+ "name": "ADCINB4/COMP2B/AIO12",+ "type": "input",+ "description": "ADC Group B, channel 4 analog input, also comparator 2B input and digital AIO12."+ },+ {+ "number": "33",+ "name": "ADCINB5",+ "type": "input",+ "description": "ADC Group B, channel 5 analog input."+ },+ {+ "number": "34",+ "name": "ADCINB6/COMP3B/AIO14",+ "type": "input",+ "description": "ADC Group B, channel 6 analog input, also comparator 3B input and digital AIO14."+ },+ {+ "number": "35",+ "name": "ADCINB7",+ "type": "input",+ "description": "ADC Group B, channel 7 analog input."+ },+ {+ "number": "36",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "37",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground."+ },+ {+ "number": "38",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin."+ },+ {+ "number": "39",+ "name": "GPIO25/ECAP2/EQEP2B/SPISOMIB",+ "type": "bidirectional",+ "description": "General-purpose I/O 25 (tri-state) with alternates ECAP2, EQEP2 input B (PZ/PZP only) and SPI-B slave-out/master-in."+ },+ {+ "number": "40",+ "name": "GPIO31/CANTXA/EQEP2S/EPWM8A",+ "type": "bidirectional",+ "description": "General-purpose I/O 31 (tri-state) with alternates eCAN-A transmit, EQEP2 strobe (PZ/PZP only) and EPWM8A output."+ },+ {+ "number": "41",+ "name": "GPIO30/CANRXA/EQEP2I/EPWM7A",+ "type": "bidirectional",+ "description": "General-purpose I/O 30 (tri-state) with alternates eCAN-A receive, EQEP2 index (PZ/PZP only) and EPWM7A output."+ },+ {+ "number": "42",+ "name": "GPIO50/EQEP1A/MDXA/TZ1",+ "type": "bidirectional",+ "description": "General-purpose I/O 50 (tri-state) with alternates EQEP1 input A, McBSP-A transmit data and TZ1 trip-zone input; PZ/PZP only."+ },+ {+ "number": "43",+ "name": "GPIO29/SCITXDA/SCLA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 29 (tri-state) with alternates SCI-A transmit data, I2C clock open-drain (SCLA) and TZ3 trip-zone input."+ },+ {+ "number": "44",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose I/O 12 (tri-state) with alternates TZ1 trip-zone input, SCI-A transmit data and SPI-B slave-in/master-out."+ },+ {+ "number": "45",+ "name": "TEST2",+ "type": "bidirectional",+ "description": "Reserved for TI test use; must be left unconnected."+ },+ {+ "number": "46",+ "name": "VDD3VFL",+ "type": "power_in",+ "description": "3.3-V flash core power pin; this pin should be connected to 3.3 V at all times."+ },+ {+ "number": "47",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "48",+ "name": "GPIO51/EQEP1B/MDRA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 51 (tri-state) with alternates EQEP1 input B, McBSP-A receive data and TZ2 trip-zone input; PZ/PZP only."+ },+ {+ "number": "49",+ "name": "GPIO9/EPWM5B/SCITXDB/ECAP3",+ "type": "bidirectional",+ "description": "General-purpose I/O 9 (tri-state) with alternates EPWM5B output, SCI-B transmit data and ECAP3 capture I/O."+ },+ {+ "number": "50",+ "name": "GPIO28/SCIRXDA/SDAA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 28 (tri-state) with alternates SCI-A receive data, I2C data open-drain (SDAA) and TZ2 trip-zone input."+ },+ {+ "number": "51",+ "name": "GPIO18/SPICLKA/SCITXDB/XCLKOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 18 (tri-state) with alternates SPI-A clock, SCI-B transmit data and XCLKOUT (SYSCLKOUT/4 at reset); XCLKOUT requires the GPIO18 mux set to XCLKOUT."+ },+ {+ "number": "52",+ "name": "GPIO17/SPISOMIA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 17 (tri-state) with alternates SPI-A slave-out/master-in and TZ3 trip-zone input."+ },+ {+ "number": "53",+ "name": "GPIO52/EQEP1S/MCLKXA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 52 (tri-state) with alternates EQEP1 strobe, McBSP-A transmit clock and TZ3 trip-zone input; PZ/PZP only."+ },+ {+ "number": "54",+ "name": "GPIO8/EPWM5A/ADCSOCAO",+ "type": "bidirectional",+ "description": "General-purpose I/O 8 (tri-state) with alternates EPWM5A output and HRPWM channel and ADC start-of-conversion A output."+ },+ {+ "number": "55",+ "name": "GPIO16/SPISIMOA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 16 (tri-state) with alternates SPI-A slave-in/master-out and TZ2 trip-zone input."+ },+ {+ "number": "56",+ "name": "GPIO44/MFSRA/SCIRXDB/EPWM7B",+ "type": "bidirectional",+ "description": "General-purpose I/O 44 (tri-state) with alternates McBSP-A receive frame sync, SCI-B receive data and EPWM7B output; PZ/PZP only."+ },+ {+ "number": "57",+ "name": "GPIO7/EPWM4B/SCIRXDA/ECAP2",+ "type": "bidirectional",+ "description": "General-purpose I/O 7 (tri-state) with alternates EPWM4B output, SCI-A receive data and ECAP2 capture I/O."+ },+ {+ "number": "58",+ "name": "GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO",+ "type": "bidirectional",+ "description": "General-purpose I/O 6 (tri-state) with alternates EPWM4A output and HRPWM channel, ePWM sync input and ePWM sync output."+ },+ {+ "number": "59",+ "name": "X2",+ "type": "output",+ "description": "On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 must be left unconnected if not used."+ },+ {+ "number": "60",+ "name": "X1",+ "type": "input",+ "description": "On-chip 1.8-V crystal oscillator input; a quartz crystal or ceramic resonator is connected across X1 and X2, and the pin must be tied to GND if not used."+ },+ {+ "number": "61",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin."+ },+ {+ "number": "62",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "63",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground."+ },+ {+ "number": "64",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose I/O 19 (tri-state) with alternates external oscillator input XCLKIN (path not gated by the mux), SPI-A slave transmit enable, SCI-B receive data and ECAP1; glitches during VREG power-up."+ },+ {+ "number": "65",+ "name": "GPIO53/EQEP1I/MFSXA",+ "type": "bidirectional",+ "description": "General-purpose I/O 53 (tri-state) with alternates EQEP1 index and McBSP-A transmit frame sync; PZ/PZP only."+ },+ {+ "number": "66",+ "name": "GPIO39",+ "type": "bidirectional",+ "description": "General-purpose I/O 39 (tri-state) with no peripheral alternate function listed for this pin."+ },+ {+ "number": "67",+ "name": "GPIO38/XCLKIN/TCK",+ "type": "bidirectional",+ "description": "General-purpose I/O 38 (tri-state) with alternates XCLKIN external oscillator input and JTAG TCK (internal pullup); TCK function is active during JTAG debug."+ },+ {+ "number": "68",+ "name": "GPIO34/COMP2OUT/COMP3OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 34 (tri-state) with alternates COMP2OUT and COMP3OUT comparator direct outputs; not glitch-free during power-up when VREG is used."+ },+ {+ "number": "69",+ "name": "GPIO54/SPISIMOA/EQEP2A/HRCAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 54 (tri-state) with alternates SPI-A slave-in/master-out, EQEP2 input A and HRCAP1 high-resolution capture input; PZ/PZP only."+ },+ {+ "number": "70",+ "name": "GPIO37/TDO",+ "type": "tri_state",+ "description": "General-purpose I/O 37 with JTAG scan data output TDO, shifted out on the falling edge of TCK with 8-mA drive."+ },+ {+ "number": "71",+ "name": "GPIO35/TDI",+ "type": "bidirectional",+ "description": "General-purpose I/O 35 with JTAG test data input TDI, which has an internal pullup and is clocked on the rising edge of TCK."+ },+ {+ "number": "72",+ "name": "GPIO36/TMS",+ "type": "bidirectional",+ "description": "General-purpose I/O 36 with JTAG test-mode select TMS, which has an internal pullup and is clocked on the rising edge of TCK."+ },+ {+ "number": "73",+ "name": "GPIO11/EPWM6B/SCIRXDB/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 11 (tri-state) with alternates EPWM6B output, SCI-B receive data and ECAP1 capture I/O."+ },+ {+ "number": "74",+ "name": "GPIO10/EPWM6A/ADCSOCBO",+ "type": "bidirectional",+ "description": "General-purpose I/O 10 (tri-state) with alternates EPWM6A output and HRPWM channel and ADC start-of-conversion B output."+ },+ {+ "number": "75",+ "name": "GPIO55/SPISOMIA/EQEP2B/HRCAP2",+ "type": "bidirectional",+ "description": "General-purpose I/O 55 (tri-state) with alternates SPI-A slave-out/master-in, EQEP2 input B and HRCAP2 capture input; PZ/PZP only."+ },+ {+ "number": "76",+ "name": "GPIO41/EPWM7B/SCIRXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 41 (tri-state) with alternates EPWM7B output and SCI-B receive data; PZ/PZP only."+ },+ {+ "number": "77",+ "name": "GPIO27/HRCAP2/EQEP2S/SPISTEB/USB0DM",+ "type": "bidirectional",+ "description": "General-purpose I/O 27 (tri-state) with alternates HRCAP2, EQEP2 strobe, SPI-B slave transmit enable and USB0DM negative differential signal (enabled via USBIOEN in GPACTRL2)."+ },+ {+ "number": "78",+ "name": "GPIO26/ECAP3/EQEP2I/SPICLKB/USB0DP",+ "type": "bidirectional",+ "description": "General-purpose I/O 26 (tri-state) with alternates ECAP3, EQEP2 index, SPI-B clock and USB0DP positive differential signal (enabled via USBIOEN in GPACTRL2); glitches during VREG power-up."+ },+ {+ "number": "79",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin."+ },+ {+ "number": "80",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "81",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground."+ },+ {+ "number": "82",+ "name": "GPIO40/EPWM7A/SCITXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 40 (tri-state) with alternates EPWM7A output and SCI-B transmit data; PZ/PZP only."+ },+ {+ "number": "83",+ "name": "GPIO3/EPWM2B/SPISOMIA/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 3 (tri-state) with alternates EPWM2B output, SPI-A slave-out/master-in and COMP2OUT comparator 2 direct output."+ },+ {+ "number": "84",+ "name": "GPIO2/EPWM2A",+ "type": "bidirectional",+ "description": "General-purpose I/O 2 (tri-state) with alternate function EPWM2A output and HRPWM channel."+ },+ {+ "number": "85",+ "name": "GPIO56/SPICLKA/EQEP2I/HRCAP3",+ "type": "bidirectional",+ "description": "General-purpose I/O 56 (tri-state) with alternates SPI-A clock, EQEP2 index and HRCAP3 capture input; PZ/PZP only."+ },+ {+ "number": "86",+ "name": "GPIO1/EPWM1B/COMP1OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 1 (tri-state) with alternates EPWM1B output and COMP1OUT comparator 1 direct output."+ },+ {+ "number": "87",+ "name": "GPIO0/EPWM1A",+ "type": "bidirectional",+ "description": "General-purpose I/O 0 (tri-state) with alternate function EPWM1A output and HRPWM channel."+ },+ {+ "number": "88",+ "name": "GPIO15/ECAP2/SCIRXDB/SPISTEB",+ "type": "bidirectional",+ "description": "General-purpose I/O 15 (tri-state) with alternates ECAP2 capture I/O, SCI-B receive data and SPI-B slave transmit enable."+ },+ {+ "number": "89",+ "name": "GPIO57",+ "type": "bidirectional",+ "description": "General-purpose I/O 57 (tri-state) with alternates SPI-A slave transmit enable, EQEP2 strobe and HRCAP4 capture input; PZ/PZP only."+ },+ {+ "number": "90",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal voltage regulator enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or to VDDIO to disable it and use an external 1.8-V supply."+ },+ {+ "number": "91",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground."+ },+ {+ "number": "92",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "93",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin."+ },+ {+ "number": "94",+ "name": "GPIO58/MCLKRA/SCITXDB/EPWM7A",+ "type": "bidirectional",+ "description": "General-purpose I/O 58 (tri-state) with alternates McBSP-A receive clock, SCI-B transmit data and EPWM7A output; PZ/PZP only."+ },+ {+ "number": "95",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "General-purpose I/O 13 (tri-state) with alternates TZ2 trip-zone input and SPI-B slave-out/master-in."+ },+ {+ "number": "96",+ "name": "GPIO14",+ "type": "bidirectional",+ "description": "General-purpose I/O 14 (tri-state) with alternates TZ3 trip-zone input, SCI-B transmit data and SPI-B clock."+ },+ {+ "number": "97",+ "name": "GPIO24/ECAP1/EQEP2A/SPISIMOB",+ "type": "bidirectional",+ "description": "General-purpose I/O 24 (tri-state) with alternates ECAP1, EQEP2 input A (PZ/PZP only) and SPI-B slave-in/master-out."+ },+ {+ "number": "98",+ "name": "GPIO22/EQEP1S/MCLKXA/SCITXDB",+ "type": "bidirectional",+ "description": "General-purpose I/O 22 (tri-state) with alternates EQEP1 strobe, McBSP-A transmit clock and SCI-B transmit data."+ },+ {+ "number": "99",+ "name": "GPIO32/SDAA/EPWMSYNCI/ADCSOCAO",+ "type": "bidirectional",+ "description": "General-purpose I/O 32 (tri-state) with alternates I2C data open-drain (SDAA), ePWM sync input and ADC start-of-conversion A output."+ },+ {+ "number": "100",+ "name": "GPIO33/SCLA/EPWMSYNCO/ADCSOCBO",+ "type": "bidirectional",+ "description": "General-purpose I/O 33 (tri-state) with alternates I2C clock open-drain (SCLA), ePWM sync output and ADC start-of-conversion B output."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pin diagram text extraction (page 10) is scrambled, so pin numbers were taken from the Signal De; The 100-pin variant uses the first number column in the signal table (shared by PZ and PZP). The sec; Multi-function pins with JTAG/clock aliases: pin 64 (GPIO19) and pin 67 (GPIO38) both carry XCLKIN; "+ ],+ "pages_sent": 43,+ "cost_usd": 0.3558,+ "at": "2026-10-08T02:01:46"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f28062f",+ "pages": 206,+ "sha256": "3033efed856fc72a",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 100,+ "described": 100,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tms320f28066pzt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16,+ 16,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "51720097260ffba41c3062f85f67623721102fa535901c47cb555a1f444feeb3",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tms320f28066pzt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16,+ 16,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7b8411434794ae17b76df84a59bb974455d035e25bff5a153135bc66c6be1988",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}