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Set visibility: public

Ray ·90ba7f3cf5 · ·parent 52ade47
1 file changed +11−8
page.json+11−8
@@ -68,7 +68,7 @@         "number": "7",         "name": "VDD",         "type": "power_in",-        "description": "CPU and logic digital 1.8 V supply. Place a 1.2 \u00b5F (or larger) decoupling capacitor between each VDD pin and ground when using the internal VREG."+        "description": "CPU and logic digital 1.8 V supply. Place a 1.2 µF (or larger) decoupling capacitor between each VDD pin and ground when using the internal VREG."       },       {         "number": "8",@@ -80,13 +80,13 @@         "number": "9",         "name": "XRS",         "type": "bidirectional",-        "description": "Device reset input and watchdog reset output. Open-drain with internal pull-up; connect a 2.2 k\u03a9-10 k\u03a9 pull-up to VDDIO. Optional 100 nF or smaller noise-filter cap to VSS."+        "description": "Device reset input and watchdog reset output. Open-drain with internal pull-up; connect a 2.2 kΩ-10 kΩ pull-up to VDDIO. Optional 100 nF or smaller noise-filter cap to VSS."       },       {         "number": "10",         "name": "TRST",         "type": "input",-        "description": "JTAG test reset with internal pull-down. Must be held low during normal device operation; requires external pull-up (typically 2.2 k\u03a9) to activate JTAG. Active-high test pin."+        "description": "JTAG test reset with internal pull-down. Must be held low during normal device operation; requires external pull-up (typically 2.2 kΩ) to activate JTAG. Active-high test pin."       },       {         "number": "11",@@ -146,7 +146,7 @@         "number": "20",         "name": "VDDA",         "type": "power_in",-        "description": "Analog 3.3 V supply. Place a ~2.2 \u00b5F decoupling capacitor near this pin."+        "description": "Analog 3.3 V supply. Place a ~2.2 µF decoupling capacitor near this pin."       },       {         "number": "21",@@ -272,7 +272,7 @@         "number": "41",         "name": "GPIO18/SPICLKA/LINTXA/XCLKOUT",         "type": "bidirectional",-        "description": "GPIO18. Alt: SPI-A clock (SPICLKA, I/O), LIN transmit A (LINTXA, O), external clock output (XCLKOUT, O/Z) sourced from SYSCLKOUT with 1x/\u00bd/\u00bc divider."+        "description": "GPIO18. Alt: SPI-A clock (SPICLKA, I/O), LIN transmit A (LINTXA, O), external clock output (XCLKOUT, O/Z) sourced from SYSCLKOUT with 1x/½/¼ divider."       },       {         "number": "42",@@ -350,7 +350,7 @@         "number": "54",         "name": "VDD",         "type": "power_in",-        "description": "CPU and logic digital 1.8 V supply. 1.2 \u00b5F (or larger) decoupling per pin when using internal VREG."+        "description": "CPU and logic digital 1.8 V supply. 1.2 µF (or larger) decoupling per pin when using internal VREG."       },       {         "number": "55",@@ -458,7 +458,7 @@         "number": "72",         "name": "VDD",         "type": "power_in",-        "description": "CPU and logic digital 1.8 V supply. 1.2 \u00b5F (or larger) decoupling per pin when using internal VREG."+        "description": "CPU and logic digital 1.8 V supply. 1.2 µF (or larger) decoupling per pin when using internal VREG."       },       {         "number": "73",@@ -570,5 +570,8 @@     "docs/tms320f28035pntr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file