TMS320F28035PNTR

@@ -0,0 +1,129 @@+# TMS320F28035PNTR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)++TMS320F28035PNTR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO22/EQEP1S/LINTXA | bidirectional | GPIO22. Alt: enhanced QEP1 strobe (EQEP1S, I/O), LIN transmit A (LINTXA, O). Internal pull-up enabled after reset. |+| 2 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | GPIO32. Alt: I2C-A data open-drain (SDAA, I/OD), ePWM external sync input (EPWMSYNCI, I), ADC start-of-conversion A (ADCSOCAO, O). |+| 3 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | GPIO33. Alt: I2C-A clock open-drain (SCLA, I/OD), ePWM external sync output (EPWMSYNCO, O), ADC start-of-conversion B (ADCSOCBO, O). |+| 4 | GPIO23/EQEP1I/LINRXA | bidirectional | GPIO23. Alt: enhanced QEP1 index (EQEP1I, I/O), LIN receive A (LINRXA, I). |+| 5 | GPIO42/COMP1OUT | bidirectional | GPIO42. Alt: comparator 1 direct output (COMP1OUT, O). |+| 6 | GPIO43/COMP2OUT | bidirectional | GPIO43. Alt: comparator 2 direct output (COMP2OUT, O). |+| 7 | VDD | power_in | CPU and logic digital 1.8 V supply. Place a 1.2 µF (or larger) decoupling capacitor between each VDD pin and ground when using the internal VREG. |+| 8 | VSS | power_in | Digital ground. |+| 9 | XRS | bidirectional | Device reset input and watchdog reset output. Open-drain with internal pull-up; connect a 2.2 kΩ-10 kΩ pull-up to VDDIO. Optional 100 nF or smaller noise-filter cap to VSS. |+| 10 | TRST | input | JTAG test reset with internal pull-down. Must be held low during normal device operation; requires external pull-up (typically 2.2 kΩ) to activate JTAG. Active-high test pin. |+| 11 | ADCINA7/ADCINA6 | input | ADC group A, channel 7 input (also channel 6 input on this pin per the datasheet listing). Analog input; not 5 V tolerant. |+| 12 | COMP3A/AIO6 | bidirectional | Comparator input 3A (analog, I) / digital AIO6 (I/O). AIO pins have no internal pull-up. |+| 13 | ADCINA5/ADCINA4 | input | ADC group A, channel 5 input (also channel 4 input). Analog input; not 5 V tolerant. |+| 14 | COMP2A/AIO4 | bidirectional | Comparator input 2A (I) / digital AIO4 (I/O). AIO pins have no internal pull-up. |+| 15 | ADCINA3/ADCINA2 | input | ADC group A, channel 3 input (also channel 2 input). Analog input; not 5 V tolerant. |+| 16 | COMP1A/AIO2 | bidirectional | Comparator input 1A (I) / digital AIO2 (I/O). AIO pins have no internal pull-up. |+| 17 | ADCINA1 | input | ADC group A, channel 1 input. Analog input; not 5 V tolerant. |+| 18 | ADCINA0 | input | ADC group A, channel 0 input. On 80-pin PN, ADCINA0 has a dedicated pin (VREFHI is separate). |+| 19 | VREFHI | input | ADC external reference high - used only in ADC external reference mode. Dedicated pin on the 80-pin PN package. |+| 20 | VDDA | power_in | Analog 3.3 V supply. Place a ~2.2 µF decoupling capacitor near this pin. |+| 21 | VSSA | power_in | Analog ground. |+| 22 | VREFLO | input | ADC external reference low. Typically tied to VSSA. |+| 23 | ADCINB0 | input | ADC group B, channel 0 input. |+| 24 | ADCINB1 | input | ADC group B, channel 1 input. |+| 25 | COMP1B/AIO10 | bidirectional | Comparator input 1B (I) / digital AIO10 (I/O). |+| 26 | ADCINB3/ADCINB2 | input | ADC group B, channel 3 input (also channel 2 input). |+| 27 | COMP2B/AIO12 | bidirectional | Comparator input 2B (I) / digital AIO12 (I/O). |+| 28 | ADCINB5/ADCINB4 | input | ADC group B, channel 5 input (also channel 4 input). |+| 29 | COMP3B/AIO14 | bidirectional | Comparator input 3B (I) / digital AIO14 (I/O). |+| 30 | ADCINB7/ADCINB6 | input | ADC group B, channel 7 input (also channel 6 input). |+| 31 | GPIO27/HRCAP2/SPISTEB | bidirectional | GPIO27. Alt: high-resolution input capture 2 (HRCAP2, I), SPI-B slave transmit enable (SPISTEB, I/O). |+| 32 | GPIO31/CANTXA | bidirectional | GPIO31. Alt: CAN transmit A (CANTXA, O). |+| 33 | GPIO30/CANRXA | bidirectional | GPIO30. Alt: CAN receive A (CANRXA, I). |+| 34 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | GPIO29. Alt: SCI-A transmit data (SCITXDA, O), I2C-A clock open-drain (SCLA, I/OD), trip-zone input 3 (TZ3, I). |+| 35 | VSS | power_in | Digital ground. |+| 36 | VDDIO | power_in | Digital I/O buffer and flash 3.3 V supply. Place a decoupling capacitor at each VDDIO pin. |+| 37 | GPIO26/HRCAP1/SPICLKB | bidirectional | GPIO26. Alt: high-resolution input capture 1 (HRCAP1, I), SPI-B clock (SPICLKB, I/O). |+| 38 | TEST2 | bidirectional | Test pin reserved by TI. Must be left unconnected. |+| 39 | GPIO9/EPWM5B/LINTXA/HRCAP1 | bidirectional | GPIO9. Alt: enhanced PWM5 output B (EPWM5B, O), LIN transmit A (LINTXA, O), high-resolution input capture 1 (HRCAP1, I). |+| 40 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | GPIO28. Alt: SCI-A receive data (SCIRXDA, I), I2C-A data open-drain (SDAA, I/OD), trip-zone input 2 (TZ2, I). |+| 41 | GPIO18/SPICLKA/LINTXA/XCLKOUT | bidirectional | GPIO18. Alt: SPI-A clock (SPICLKA, I/O), LIN transmit A (LINTXA, O), external clock output (XCLKOUT, O/Z) sourced from SYSCLKOUT with 1x/½/¼ divider. |+| 42 | GPIO17/SPISOMIA/TZ3 | bidirectional | GPIO17. Alt: SPI-A slave-out master-in (SPISOMIA, I/O), trip-zone input 3 (TZ3, I). |+| 43 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | GPIO8. Alt: enhanced PWM5 output A and HRPWM channel (EPWM5A, O), ADC start-of-conversion A (ADCSOCAO, O). |+| 44 | GPIO25/SPISOMIB | bidirectional | GPIO25. Alt: SPI-B slave-out master-in (SPISOMIB, I/O). SPI-B is available on PN and RSH packages only. |+| 45 | GPIO44 | bidirectional | GPIO44 (no additional peripheral aliases on this pin). |+| 46 | GPIO16/SPISIMOA/TZ2 | bidirectional | GPIO16. Alt: SPI-A slave-in master-out (SPISIMOA, I/O), trip-zone input 2 (TZ2, I). |+| 47 | GPIO12/TZ1/SCITXDA/SPISIMOB | bidirectional | GPIO12. Alt: trip-zone input 1 (TZ1, I), SCI-A transmit data (SCITXDA, O), SPI-B slave-in master-out (SPISIMOB, I/O; PN package only). |+| 48 | GPIO41/EPWM7B | bidirectional | GPIO41. Alt: enhanced PWM7 output B (EPWM7B, O). |+| 49 | GPIO7/EPWM4B/SCIRXDA | bidirectional | GPIO7. Alt: enhanced PWM4 output B (EPWM4B, O), SCI-A receive data (SCIRXDA, I). |+| 50 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | GPIO6. Alt: enhanced PWM4 output A and HRPWM channel (EPWM4A, O), external ePWM sync input (EPWMSYNCI, I), external ePWM sync output (EPWMSYNCO, O). |+| 51 | X2 | output | On-chip crystal oscillator output. Connect a quartz crystal or ceramic resonator between X1 and X2, or leave unconnected if not used. |+| 52 | X1 | input | 1.8 V on-chip crystal oscillator input. Connect a quartz crystal or ceramic resonator between X1 and X2. Tie to GND if unused. Disable XCLKIN path via CLKCTL bit 13 when using the crystal. |+| 53 | VSS | power_in | Digital ground. |+| 54 | VDD | power_in | CPU and logic digital 1.8 V supply. 1.2 µF (or larger) decoupling per pin when using internal VREG. |+| 55 | GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 | bidirectional | GPIO19. Alt: external oscillator input (XCLKIN, I; path not gated by pin mux), SPI-A slave transmit enable (SPISTEA, I/O), LIN receive A (LINRXA, I), enhanced capture 1 (ECAP1, I/O). |+| 56 | GPIO39 | bidirectional | GPIO39 (no additional peripheral aliases on this pin). |+| 57 | GPIO38/TCK/XCLKIN | bidirectional | GPIO38 default at reset is JTAG TCK (test clock, with internal pull-up). Also can serve as external clock input (XCLKIN). Selected via TRST behavior and CLKCTL/XCLK registers. |+| 58 | GPIO37/TDO | bidirectional | GPIO37 default is JTAG TDO (test data output, O/Z, 8 mA drive). Contents of selected register shifted out on falling edge of TCK. |+| 59 | GPIO35/TDI | bidirectional | GPIO35 default is JTAG TDI (test data input, with internal pull-up). Clocked into selected register on rising edge of TCK. |+| 60 | GPIO36/TMS | bidirectional | GPIO36 default is JTAG TMS (test mode select, with internal pull-up). Clocked into TAP controller on rising edge of TCK. |+| 61 | GPIO11/EPWM6B/LINRXA/HRCAP2 | bidirectional | GPIO11. Alt: enhanced PWM6 output B (EPWM6B, O), LIN receive A (LINRXA, I), high-resolution input capture 2 (HRCAP2, I). |+| 62 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | GPIO5. Alt: enhanced PWM3 output B (EPWM3B, O), SPI-A slave-in master-out (SPISIMOA, I/O), enhanced capture 1 (ECAP1, I/O). |+| 63 | GPIO4/EPWM3A | bidirectional | GPIO4. Alt: enhanced PWM3 output A and HRPWM channel (EPWM3A, O). |+| 64 | GPIO40/EPWM7A | bidirectional | GPIO40. Alt: enhanced PWM7 output A (EPWM7A, O). |+| 65 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | GPIO10. Alt: enhanced PWM6 output A and HRPWM channel (EPWM6A, O), ADC start-of-conversion B (ADCSOCBO, O). |+| 66 | GPIO3/EPWM2B/SPISOMIA/COMP2OUT | bidirectional | GPIO3. Alt: enhanced PWM2 output B (EPWM2B, O), SPI-A slave-out master-in (SPISOMIA, I/O), comparator 2 direct output (COMP2OUT, O). |+| 67 | GPIO2/EPWM2A | bidirectional | GPIO2. Alt: enhanced PWM2 output A and HRPWM channel (EPWM2A, O). |+| 68 | GPIO1/EPWM1B/COMP1OUT | bidirectional | GPIO1. Alt: enhanced PWM1 output B (EPWM1B, O), comparator 1 direct output (COMP1OUT, O). |+| 69 | GPIO0/EPWM1A | bidirectional | GPIO0. Alt: enhanced PWM1 output A and HRPWM channel (EPWM1A, O). |+| 70 | VDDIO | power_in | Digital I/O buffer and flash 3.3 V supply. Place a decoupling capacitor at each VDDIO pin. |+| 71 | VSS | power_in | Digital ground. |+| 72 | VDD | power_in | CPU and logic digital 1.8 V supply. 1.2 µF (or larger) decoupling per pin when using internal VREG. |+| 73 | VREGENZ | input | Internal 1.8 V VREG enable (with internal pull-down). Tie to VSS to enable the internal VREG; tie to VDDIO to disable it and supply external 1.8 V. |+| 74 | GPIO34/COMP2OUT/COMP3OUT | bidirectional | GPIO34. Alt: comparator 2 direct output (COMP2OUT, O), comparator 3 direct output (COMP3OUT, O). |+| 75 | GPIO15/TZ1/LINRXA/SPISTEB | bidirectional | GPIO15. Alt: trip-zone input 1 (TZ1, I), LIN receive A (LINRXA, I), SPI-B slave transmit enable (SPISTEB, I/O). |+| 76 | GPIO13/TZ2/SPISOMIB | bidirectional | GPIO13. Alt: trip-zone input 2 (TZ2, I), SPI-B slave-out master-in (SPISOMIB, I/O). |+| 77 | GPIO14/TZ3/LINTXA/SPICLKB | bidirectional | GPIO14. Alt: trip-zone input 3 (TZ3, I), LIN transmit A (LINTXA, O), SPI-B clock (SPICLKB, I/O). |+| 78 | GPIO20/EQEP1A/COMP1OUT | bidirectional | GPIO20. Alt: enhanced QEP1 input A (EQEP1A, I), comparator 1 direct output (COMP1OUT, O). |+| 79 | GPIO21/EQEP1B/COMP2OUT | bidirectional | GPIO21. Alt: enhanced QEP1 input B (EQEP1B, I), comparator 2 direct output (COMP2OUT, O). |+| 80 | GPIO24/ECAP1/SPISIMOB | bidirectional | GPIO24. Alt: enhanced capture 1 (ECAP1, I/O), SPI-B slave-in master-out (SPISIMOB, I/O; PN and RSH packages only). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-80(12x12) |+| Category | MCU |+| Pins | 80 |++## Ordering variants++- `TMS320F28035PNTRPN`+- `TMS320F28035PNTRPNT`+- `TMS320F28035PNTRPNTR`+- `TMS320F28035PNTRPNQ`+- `TMS320F28035PNTRPNQR`+- `TMS320F28035PNTRPNS`+- `TMS320F28035PNTRPAG`+- `TMS320F28035PNTRPAGT`+- `TMS320F28035PNTRPAGQ`+- `TMS320F28035PNTRPAGS`+- `TMS320F28035PNTRRSH`++## CAD (KiCad official)++- Symbol: `TMS320F28035PNTR`+- Footprint: `Package_QFP:LQFP-80_12x12mm_P0.5mm`+- 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](docs/tms320f28035pntr-datasheet.pdf) (169 pp, sha256 `a49f83b9ffcd2982`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320f28035pntr-datasheet.pdf)