component
TMS320F28035PNTR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (DIGIKEY_PN TMS320F28035PNTR-ND, LCSC_PN C2055860). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+32−10
page.json+11−8@@ -26,7 +26,10 @@ "model_3d_step": "tms320f28035pntr.step", "lbr": "tms320f28035pntr.lbr" },- "distributor_links": {},+ "distributor_links": {+ "digikey": "TMS320F28035PNTR-ND",+ "lcsc": "C2055860"+ }, "pins": [ { "number": "1",@@ -68,7 +71,7 @@ "number": "7", "name": "VDD", "type": "power_in",- "description": "CPU and logic digital 1.8 V supply. Place a 1.2 µF (or larger) decoupling capacitor between each VDD pin and ground when using the internal VREG."+ "description": "CPU and logic digital 1.8 V supply. Place a 1.2 \u00b5F (or larger) decoupling capacitor between each VDD pin and ground when using the internal VREG." }, { "number": "8",@@ -80,13 +83,13 @@ "number": "9", "name": "XRS", "type": "bidirectional",- "description": "Device reset input and watchdog reset output. Open-drain with internal pull-up; connect a 2.2 kΩ-10 kΩ pull-up to VDDIO. Optional 100 nF or smaller noise-filter cap to VSS."+ "description": "Device reset input and watchdog reset output. Open-drain with internal pull-up; connect a 2.2 k\u03a9-10 k\u03a9 pull-up to VDDIO. Optional 100 nF or smaller noise-filter cap to VSS." }, { "number": "10", "name": "TRST", "type": "input",- "description": "JTAG test reset with internal pull-down. Must be held low during normal device operation; requires external pull-up (typically 2.2 kΩ) to activate JTAG. Active-high test pin."+ "description": "JTAG test reset with internal pull-down. Must be held low during normal device operation; requires external pull-up (typically 2.2 k\u03a9) to activate JTAG. Active-high test pin." }, { "number": "11",@@ -146,7 +149,7 @@ "number": "20", "name": "VDDA", "type": "power_in",- "description": "Analog 3.3 V supply. Place a ~2.2 µF decoupling capacitor near this pin."+ "description": "Analog 3.3 V supply. Place a ~2.2 \u00b5F decoupling capacitor near this pin." }, { "number": "21",@@ -272,7 +275,7 @@ "number": "41", "name": "GPIO18/SPICLKA/LINTXA/XCLKOUT", "type": "bidirectional",- "description": "GPIO18. Alt: SPI-A clock (SPICLKA, I/O), LIN transmit A (LINTXA, O), external clock output (XCLKOUT, O/Z) sourced from SYSCLKOUT with 1x/½/¼ divider."+ "description": "GPIO18. Alt: SPI-A clock (SPICLKA, I/O), LIN transmit A (LINTXA, O), external clock output (XCLKOUT, O/Z) sourced from SYSCLKOUT with 1x/\u00bd/\u00bc divider." }, { "number": "42",@@ -350,7 +353,7 @@ "number": "54", "name": "VDD", "type": "power_in",- "description": "CPU and logic digital 1.8 V supply. 1.2 µF (or larger) decoupling per pin when using internal VREG."+ "description": "CPU and logic digital 1.8 V supply. 1.2 \u00b5F (or larger) decoupling per pin when using internal VREG." }, { "number": "55",@@ -458,7 +461,7 @@ "number": "72", "name": "VDD", "type": "power_in",- "description": "CPU and logic digital 1.8 V supply. 1.2 µF (or larger) decoupling per pin when using internal VREG."+ "description": "CPU and logic digital 1.8 V supply. 1.2 \u00b5F (or larger) decoupling per pin when using internal VREG." }, { "number": "73",
tms320f28035pntr.lbr+21−2@@ -134,6 +134,18 @@ <smd name="78" x="-3.7500" y="6.6875" dx="0.2500" dy="1.4750" layer="1"/> <smd name="79" x="-4.2500" y="6.6875" dx="0.2500" dy="1.4750" layer="1"/> <smd name="80" x="-4.7500" y="6.6875" dx="0.2500" dy="1.4750" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-6.7500" y="5.1400"/>+ <vertex x="-7.0900" y="5.6100"/>+ <vertex x="-6.4100" y="5.6100"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-5.0000" y="6.0000"/>+ <vertex x="6.0000" y="6.0000"/>+ <vertex x="6.0000" y="-6.0000"/>+ <vertex x="-6.0000" y="-6.0000"/>+ <vertex x="-6.0000" y="5.0000"/>+ </polygon> <wire x1="-6.1100" y1="6.1100" x2="-5.1350" y2="6.1100" width="0.1200" layer="21"/> <wire x1="-6.1100" y1="5.1350" x2="-6.1100" y2="6.1100" width="0.1200" layer="21"/> <wire x1="-6.1100" y1="-6.1100" x2="-6.1100" y2="-5.1350" width="0.1200" layer="21"/>@@ -144,7 +156,7 @@ <wire x1="6.1100" y1="-6.1100" x2="5.1350" y2="-6.1100" width="0.1200" layer="21"/> <text x="0" y="8.025" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-8.025" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-6.7500" y="5.1400"/><vertex x="-7.0900" y="5.6100"/><vertex x="-6.4100" y="5.6100"/></polygon></package>+</package> </packages> <symbols> <symbol name="TMS320F28035PNTR">@@ -326,7 +338,14 @@ <connect gate="G$1" pin="GPIO17/SPISOMIA/TZ3" pad="42"/> <connect gate="G$1" pin="GPIO18/SPICLKA/LINTXA/XCLKOUT" pad="41"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="TMS320F28035PNTR" constant="no"/>+ <attribute name="MANUFACTURER" value="Texas Instruments" constant="no"/>+ <attribute name="DIGIKEY_PN" value="TMS320F28035PNTR-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C2055860" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>