component
TMS320F28027FPTT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# TMS320F28027FPTT++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)++TMS320F28027FPTT from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 (GPIO function is default at reset, I/O/Z); alternate functions are SCI-A transmit data (SCITXDA), I2C-A clock (SCLA), and Trip-Zone 3 input (TZ3). |+| 2 | TRST | input | JTAG test reset input with an internal pull-down; must be held low during normal device operation and requires an external pull-up resistor (typically 2.2kΩ) sized for the debug pod driver strength. |+| 3 | XRS | bidirectional | Open-drain device reset (input) and watchdog reset (output) with internal pull-up; driven low by POR/BOR or for 512 OSCCLK cycles during a watchdog reset, requiring an external 2.2kΩ-10kΩ pull-up to VDDIO. |+| 4 | ADCINA6/AIO6 | input | ADC group A channel 6 analog input, alternately usable as digital I/O AIO6. |+| 5 | ADCINA4/COMP2A/AIO4 | input | ADC group A channel 4 analog input, alternately comparator 2 input A (COMP2A, available only on the 48-pin package) or digital I/O AIO4. |+| 6 | ADCINA7 | input | ADC group A, channel 7 analog input. |+| 7 | ADCINA3 | input | ADC group A, channel 3 analog input. |+| 8 | ADCINA1 | input | ADC group A, channel 1 analog input. |+| 9 | ADCINA2/COMP1A/AIO2 | input | ADC group A channel 2 analog input, alternately comparator 1 input A (COMP1A) or digital I/O AIO2. |+| 10 | ADCINA0/VREFHI | input | ADC group A channel 0 analog input; also the external high ADC reference (VREFHI), used only in external-reference mode and which must not exceed VDDA. |+| 11 | VDDA | power_in | Analog power-supply pin; a 2.2µF decoupling capacitor (typical) should be placed near this pin. |+| 12 | VSSA/VREFLO | power_in | Analog ground pin; also the low ADC external reference (VREFLO), which is always tied to ground. |+| 13 | ADCINB1 | input | ADC group B, channel 1 analog input. |+| 14 | ADCINB2/COMP1B/AIO10 | input | ADC group B channel 2 analog input, alternately comparator 1 input B (COMP1B) or digital I/O AIO10. |+| 15 | ADCINB3 | input | ADC group B, channel 3 analog input. |+| 16 | ADCINB4/COMP2B/AIO12 | input | ADC group B channel 4 analog input, alternately comparator 2 input B (COMP2B, available only on the 48-pin package) or digital I/O AIO12. |+| 17 | ADCINB6/AIO14 | input | ADC group B channel 6 analog input, alternately usable as digital I/O AIO14. |+| 18 | ADCINB7 | input | ADC group B, channel 7 analog input. |+| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34 (GPIO default at reset); alternate function is the direct output of comparator 2 (COMP2OUT, available only on the 48-pin package). |+| 20 | GPIO35 (TDI) | input | JTAG test data input (TDI) with internal pull-up, shifted into the selected instruction/data register on the rising edge of TCK; also usable as GPIO35. |+| 21 | GPIO36 (TMS) | input | JTAG test mode select (TMS) serial control input with internal pull-up, latched into the TAP controller on the rising edge of TCK; also usable as GPIO36. |+| 22 | GPIO37 (TDO) | output | JTAG scan test data output (TDO, 8mA drive), shifted out of the selected register on the falling edge of TCK; also usable as GPIO37. |+| 23 | GPIO38/XCLKIN (TCK) | input | JTAG test clock (TCK, default function) with internal pull-up; also usable as GPIO38 or as the external oscillator clock input (XCLKIN). |+| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18 (GPIO default at reset); alternate functions are SPI-A clock (SPICLKA), SCI-A transmit data (SCITXDA), or the buffered output clock XCLKOUT derived from SYSCLKOUT. |+| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19 (GPIO default at reset); alternate functions are the external oscillator clock input (XCLKIN), SPI-A slave transmit enable (SPISTEA), SCI-A receive data (SCIRXDA), or enhanced capture input 1 (ECAP1). |+| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 (GPIO default at reset); alternate functions are SPI-A slave-out/master-in data (SPISOMIA) or Trip-Zone 3 input (TZ3). |+| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 (GPIO default at reset); alternate functions are SPI-A slave-in/master-out data (SPISIMOA) or Trip-Zone 2 input (TZ2). |+| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 (I/O/Z, GPIO default at reset); alternate functions are enhanced PWM1 output B (EPWM1B) or the direct output of comparator 1 (COMP1OUT). |+| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 (I/O/Z, GPIO default at reset); alternate function is enhanced PWM1 output A and HRPWM channel (EPWM1A). |+| 30 | TEST | unconnected | Test pin reserved for TI; must be left unconnected. |+| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 (GPIO default at reset); alternate functions are I2C-A data (SDAA), ePWM sync input (EPWMSYNCI), or ADC start-of-conversion A output (ADCSOCAO). |+| 32 | VDD | power_in | CPU and digital logic power-supply pin; when the internal VREG is used, place a 1.2µF capacitor between each VDD pin and ground (a larger value may also be used). |+| 33 | VSS | power_in | Digital ground pin. |+| 34 | VREGENZ | input | Internal voltage regulator (VREG) enable, with internal pull-down; tie directly to VSS (low) to enable the internal 1.8V VREG, or tie directly to VDDIO (high) to disable VREG and use an external 1.8V supply. |+| 35 | VDDIO | power_in | Digital I/O buffer and flash power-supply pin, used as a single supply when VREG is enabled; a decoupling capacitor sized per the system voltage-regulation solution should be placed on this pin. |+| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 (GPIO default at reset); alternate functions are I2C-A clock (SCLA), ePWM sync output (EPWMSYNCO), or ADC start-of-conversion B output (ADCSOCBO). |+| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 (GPIO default at reset); alternate function is enhanced PWM2 output A and HRPWM channel (EPWM2A). |+| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3 (GPIO default at reset); alternate functions are enhanced PWM2 output B (EPWM2B) or the direct output of comparator 2 (COMP2OUT, available only on the 48-pin package). |+| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 (GPIO default at reset); alternate function is enhanced PWM3 output A and HRPWM channel (EPWM3A). |+| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5 (GPIO default at reset); alternate functions are enhanced PWM3 output B (EPWM3B) or enhanced capture input 1 (ECAP1). |+| 41 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 (GPIO default at reset); alternate functions are enhanced PWM4 output A (EPWM4A), ePWM sync input (EPWMSYNCI), or ePWM sync output (EPWMSYNCO). |+| 42 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7 (GPIO default at reset); alternate functions are enhanced PWM4 output B (EPWM4B) or SCI-A receive data (SCIRXDA). |+| 43 | VDD | power_in | CPU and digital logic power-supply pin; when the internal VREG is used, place a 1.2µF capacitor between each VDD pin and ground (a larger value may also be used). |+| 44 | VSS | power_in | Digital ground pin. |+| 45 | X1 | input | 1.8V on-chip crystal-oscillator input; a quartz crystal or ceramic resonator must be connected between X1 and X2 to use this oscillator, otherwise tie to GND and disable the XCLKIN path via the CLKCTL register. |+| 46 | X2 | output | On-chip crystal-oscillator output; a quartz crystal or ceramic resonator must be connected between X1 and X2, and this pin must be left unconnected if unused. |+| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12 (GPIO default at reset); alternate functions are Trip-Zone 1 input (TZ1) or SCI-A transmit data (SCITXDA). |+| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 (GPIO default at reset); alternate functions are SCI-A receive data (SCIRXDA), I2C-A data (SDAA), or Trip-Zone 2 input (TZ2). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-48(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `TMS320F28027FPTT`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `tms320f28027fptt-etched.step` / `tms320f28027fptt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28027fptt.step` / `tms320f28027fptt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28027f) (147 pp, sha256 `b90c388f4142c4b5`, retrieved 2026-09-29, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320f28027fptt-datasheet.pdf)
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Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320f28027fptt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320f28027fptt.kicad_sym",+ "tms320f28027fptt.kicad_mod",+ "tms320f28027fptt.glb",+ "tms320f28027fptt.step",+ "tms320f28027fptt.lbr",+ "docs/hero.png",+ "docs/tms320f28027fptt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "TMS320F28027FPTT",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f28027f",+ "parts": {+ "symbol": "tms320f28027fptt.kicad_sym",+ "footprint": "tms320f28027fptt.kicad_mod",+ "model_3d": "tms320f28027fptt-etched.glb",+ "model_3d_plain": "tms320f28027fptt.glb",+ "model_3d_step": "tms320f28027fptt-etched.step",+ "model_3d_step_plain": "tms320f28027fptt.step",+ "lbr": "tms320f28027fptt.lbr"+ },+ "distributor_links": {+ "lcsc": "C88030",+ "digikey": "296-36409-ND",+ "mouser": "595-TMS320F28027FPTT"+ },+ "distributor_check": {+ "checked_at": "2026-09-29T16:25:21Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-36409-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TMS320F28027FPTT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO29/SCITXDA/SCLA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 29 (GPIO function is default at reset, I/O/Z); alternate functions are SCI-A transmit data (SCITXDA), I2C-A clock (SCLA), and Trip-Zone 3 input (TZ3)."+ },+ {+ "number": "2",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset input with an internal pull-down; must be held low during normal device operation and requires an external pull-up resistor (typically 2.2kΩ) sized for the debug pod driver strength."+ },+ {+ "number": "3",+ "name": "XRS",+ "type": "bidirectional",+ "description": "Open-drain device reset (input) and watchdog reset (output) with internal pull-up; driven low by POR/BOR or for 512 OSCCLK cycles during a watchdog reset, requiring an external 2.2kΩ-10kΩ pull-up to VDDIO."+ },+ {+ "number": "4",+ "name": "ADCINA6/AIO6",+ "type": "input",+ "description": "ADC group A channel 6 analog input, alternately usable as digital I/O AIO6."+ },+ {+ "number": "5",+ "name": "ADCINA4/COMP2A/AIO4",+ "type": "input",+ "description": "ADC group A channel 4 analog input, alternately comparator 2 input A (COMP2A, available only on the 48-pin package) or digital I/O AIO4."+ },+ {+ "number": "6",+ "name": "ADCINA7",+ "type": "input",+ "description": "ADC group A, channel 7 analog input."+ },+ {+ "number": "7",+ "name": "ADCINA3",+ "type": "input",+ "description": "ADC group A, channel 3 analog input."+ },+ {+ "number": "8",+ "name": "ADCINA1",+ "type": "input",+ "description": "ADC group A, channel 1 analog input."+ },+ {+ "number": "9",+ "name": "ADCINA2/COMP1A/AIO2",+ "type": "input",+ "description": "ADC group A channel 2 analog input, alternately comparator 1 input A (COMP1A) or digital I/O AIO2."+ },+ {+ "number": "10",+ "name": "ADCINA0/VREFHI",+ "type": "input",+ "description": "ADC group A channel 0 analog input; also the external high ADC reference (VREFHI), used only in external-reference mode and which must not exceed VDDA."+ },+ {+ "number": "11",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power-supply pin; a 2.2µF decoupling capacitor (typical) should be placed near this pin."+ },+ {+ "number": "12",+ "name": "VSSA/VREFLO",+ "type": "power_in",+ "description": "Analog ground pin; also the low ADC external reference (VREFLO), which is always tied to ground."+ },+ {+ "number": "13",+ "name": "ADCINB1",+ "type": "input",+ "description": "ADC group B, channel 1 analog input."+ },+ {+ "number": "14",+ "name": "ADCINB2/COMP1B/AIO10",+ "type": "input",+ "description": "ADC group B channel 2 analog input, alternately comparator 1 input B (COMP1B) or digital I/O AIO10."+ },+ {+ "number": "15",+ "name": "ADCINB3",+ "type": "input",+ "description": "ADC group B, channel 3 analog input."+ },+ {+ "number": "16",+ "name": "ADCINB4/COMP2B/AIO12",+ "type": "input",+ "description": "ADC group B channel 4 analog input, alternately comparator 2 input B (COMP2B, available only on the 48-pin package) or digital I/O AIO12."+ },+ {+ "number": "17",+ "name": "ADCINB6/AIO14",+ "type": "input",+ "description": "ADC group B channel 6 analog input, alternately usable as digital I/O AIO14."+ },+ {+ "number": "18",+ "name": "ADCINB7",+ "type": "input",+ "description": "ADC group B, channel 7 analog input."+ },+ {+ "number": "19",+ "name": "GPIO34/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 34 (GPIO default at reset); alternate function is the direct output of comparator 2 (COMP2OUT, available only on the 48-pin package)."+ },+ {+ "number": "20",+ "name": "GPIO35 (TDI)",+ "type": "input",+ "description": "JTAG test data input (TDI) with internal pull-up, shifted into the selected instruction/data register on the rising edge of TCK; also usable as GPIO35."+ },+ {+ "number": "21",+ "name": "GPIO36 (TMS)",+ "type": "input",+ "description": "JTAG test mode select (TMS) serial control input with internal pull-up, latched into the TAP controller on the rising edge of TCK; also usable as GPIO36."+ },+ {+ "number": "22",+ "name": "GPIO37 (TDO)",+ "type": "output",+ "description": "JTAG scan test data output (TDO, 8mA drive), shifted out of the selected register on the falling edge of TCK; also usable as GPIO37."+ },+ {+ "number": "23",+ "name": "GPIO38/XCLKIN (TCK)",+ "type": "input",+ "description": "JTAG test clock (TCK, default function) with internal pull-up; also usable as GPIO38 or as the external oscillator clock input (XCLKIN)."+ },+ {+ "number": "24",+ "name": "GPIO18/SPICLKA/SCITXDA/XCLKOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 18 (GPIO default at reset); alternate functions are SPI-A clock (SPICLKA), SCI-A transmit data (SCITXDA), or the buffered output clock XCLKOUT derived from SYSCLKOUT."+ },+ {+ "number": "25",+ "name": "GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 19 (GPIO default at reset); alternate functions are the external oscillator clock input (XCLKIN), SPI-A slave transmit enable (SPISTEA), SCI-A receive data (SCIRXDA), or enhanced capture input 1 (ECAP1)."+ },+ {+ "number": "26",+ "name": "GPIO17/SPISOMIA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 17 (GPIO default at reset); alternate functions are SPI-A slave-out/master-in data (SPISOMIA) or Trip-Zone 3 input (TZ3)."+ },+ {+ "number": "27",+ "name": "GPIO16/SPISIMOA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 16 (GPIO default at reset); alternate functions are SPI-A slave-in/master-out data (SPISIMOA) or Trip-Zone 2 input (TZ2)."+ },+ {+ "number": "28",+ "name": "GPIO1/EPWM1B/COMP1OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 1 (I/O/Z, GPIO default at reset); alternate functions are enhanced PWM1 output B (EPWM1B) or the direct output of comparator 1 (COMP1OUT)."+ },+ {+ "number": "29",+ "name": "GPIO0/EPWM1A",+ "type": "bidirectional",+ "description": "General-purpose I/O 0 (I/O/Z, GPIO default at reset); alternate function is enhanced PWM1 output A and HRPWM channel (EPWM1A)."+ },+ {+ "number": "30",+ "name": "TEST",+ "type": "unconnected",+ "description": "Test pin reserved for TI; must be left unconnected."+ },+ {+ "number": "31",+ "name": "GPIO32/SDAA/EPWMSYNCI/ADCSOCAO",+ "type": "bidirectional",+ "description": "General-purpose I/O 32 (GPIO default at reset); alternate functions are I2C-A data (SDAA), ePWM sync input (EPWMSYNCI), or ADC start-of-conversion A output (ADCSOCAO)."+ },+ {+ "number": "32",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and digital logic power-supply pin; when the internal VREG is used, place a 1.2µF capacitor between each VDD pin and ground (a larger value may also be used)."+ },+ {+ "number": "33",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "34",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal voltage regulator (VREG) enable, with internal pull-down; tie directly to VSS (low) to enable the internal 1.8V VREG, or tie directly to VDDIO (high) to disable VREG and use an external 1.8V supply."+ },+ {+ "number": "35",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer and flash power-supply pin, used as a single supply when VREG is enabled; a decoupling capacitor sized per the system voltage-regulation solution should be placed on this pin."+ },+ {+ "number": "36",+ "name": "GPIO33/SCLA/EPWMSYNCO/ADCSOCBO",+ "type": "bidirectional",+ "description": "General-purpose I/O 33 (GPIO default at reset); alternate functions are I2C-A clock (SCLA), ePWM sync output (EPWMSYNCO), or ADC start-of-conversion B output (ADCSOCBO)."+ },+ {+ "number": "37",+ "name": "GPIO2/EPWM2A",+ "type": "bidirectional",+ "description": "General-purpose I/O 2 (GPIO default at reset); alternate function is enhanced PWM2 output A and HRPWM channel (EPWM2A)."+ },+ {+ "number": "38",+ "name": "GPIO3/EPWM2B/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 3 (GPIO default at reset); alternate functions are enhanced PWM2 output B (EPWM2B) or the direct output of comparator 2 (COMP2OUT, available only on the 48-pin package)."+ },+ {+ "number": "39",+ "name": "GPIO4/EPWM3A",+ "type": "bidirectional",+ "description": "General-purpose I/O 4 (GPIO default at reset); alternate function is enhanced PWM3 output A and HRPWM channel (EPWM3A)."+ },+ {+ "number": "40",+ "name": "GPIO5/EPWM3B/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 5 (GPIO default at reset); alternate functions are enhanced PWM3 output B (EPWM3B) or enhanced capture input 1 (ECAP1)."+ },+ {+ "number": "41",+ "name": "GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO",+ "type": "bidirectional",+ "description": "General-purpose I/O 6 (GPIO default at reset); alternate functions are enhanced PWM4 output A (EPWM4A), ePWM sync input (EPWMSYNCI), or ePWM sync output (EPWMSYNCO)."+ },+ {+ "number": "42",+ "name": "GPIO7/EPWM4B/SCIRXDA",+ "type": "bidirectional",+ "description": "General-purpose I/O 7 (GPIO default at reset); alternate functions are enhanced PWM4 output B (EPWM4B) or SCI-A receive data (SCIRXDA)."+ },+ {+ "number": "43",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and digital logic power-supply pin; when the internal VREG is used, place a 1.2µF capacitor between each VDD pin and ground (a larger value may also be used)."+ },+ {+ "number": "44",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "45",+ "name": "X1",+ "type": "input",+ "description": "1.8V on-chip crystal-oscillator input; a quartz crystal or ceramic resonator must be connected between X1 and X2 to use this oscillator, otherwise tie to GND and disable the XCLKIN path via the CLKCTL register."+ },+ {+ "number": "46",+ "name": "X2",+ "type": "output",+ "description": "On-chip crystal-oscillator output; a quartz crystal or ceramic resonator must be connected between X1 and X2, and this pin must be left unconnected if unused."+ },+ {+ "number": "47",+ "name": "GPIO12/TZ1/SCITXDA",+ "type": "bidirectional",+ "description": "General-purpose I/O 12 (GPIO default at reset); alternate functions are Trip-Zone 1 input (TZ1) or SCI-A transmit data (SCITXDA)."+ },+ {+ "number": "48",+ "name": "GPIO28/SCIRXDA/SDAA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 28 (GPIO default at reset); alternate functions are SCI-A receive data (SCIRXDA), I2C-A data (SDAA), or Trip-Zone 2 input (TZ2)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f28027f",+ "pages": 147,+ "sha256": "b90c388f4142c4b5",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}