component
TMS320F28022PTT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# TMS320F28022PTT++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)++TMS320F28022PTT from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 (group 2, 8 mA) with alternate SCI-A transmit, open-drain I2C-A clock, or trip-zone input 3. |+| 2 | TRST | input | JTAG test reset with internal pulldown; it must be held low during normal operation, and an external pullup (about 2.2 kΩ typical) is required so the device runs in functional mode. |+| 3 | XRS | bidirectional | Open-drain device reset input and watchdog reset output with internal pullup, driven low on power-up, brown-out and watchdog reset; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required and any noise capacitor to VSS must be 100 nF or less. |+| 4 | ADCINA6/AIO6 | bidirectional | ADC group A channel 6 analog input, also selectable as digital AIO6 (AIO pins have no internal pullup). |+| 5 | ADCINA4/COMP2A/AIO4 | bidirectional | ADC group A channel 4 input, also comparator 2A input (48-pin package only) and digital AIO4. |+| 6 | ADCINA7 | input | ADC group A channel 7 analog input. |+| 7 | ADCINA3 | input | ADC group A channel 3 analog input. |+| 8 | ADCINA1 | input | ADC group A channel 1 analog input. |+| 9 | ADCINA2/COMP1A/AIO2 | bidirectional | ADC group A channel 2 input, also comparator 1A input and digital AIO2. |+| 10 | ADCINA0/VREFHI | input | ADC group A channel 0 analog input, which doubles as external ADC reference high (VREFHI) in external-reference mode and must not exceed VDDA. |+| 11 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V (3.3 V nominal), with about 2.2 µF typical capacitor placed near this pin. |+| 12 | VSSA/VREFLO | power_in | Analog ground, also the ADC external reference low (VREFLO), which is always tied to ground. |+| 13 | ADCINB1 | input | ADC group B channel 1 analog input. |+| 14 | ADCINB2/COMP1B/AIO10 | bidirectional | ADC group B channel 2 input, also comparator 1B input and digital AIO10. |+| 15 | ADCINB3 | input | ADC group B channel 3 analog input. |+| 16 | ADCINB4/COMP2B/AIO12 | bidirectional | ADC group B channel 4 input, also comparator 2B input (48-pin package only) and digital AIO12. |+| 17 | ADCINB6/AIO14 | bidirectional | ADC group B channel 6 analog input, also digital AIO14. |+| 18 | ADCINB7 | input | ADC group B channel 7 analog input. |+| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34, also direct output of comparator 2 (48-pin only), and a boot-mode select pin sampled at reset. |+| 20 | GPIO35/TDI | bidirectional | General-purpose I/O 35, also JTAG test data input with internal pullup, sampled on the rising edge of TCK; may glitch at power-up when the internal VREG is used. |+| 21 | GPIO36/TMS | bidirectional | General-purpose I/O 36 (group 2, 8 mA), also JTAG test mode select input with internal pullup, sampled on the rising edge of TCK. |+| 22 | GPIO37/TDO | bidirectional | General-purpose I/O 37 (group 2, 8 mA), also JTAG test data output shifted out on the falling edge of TCK and a boot-mode select pin sampled at reset. |+| 23 | GPIO38/TCK/XCLKIN | bidirectional | General-purpose I/O 38, also JTAG test clock input with internal pullup and the default source for the external XCLKIN oscillator input (XCLKINSEL in XCLK register). |+| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18 (group 2, 8 mA), also SPI-A clock, SCI-A transmit, or XCLKOUT (SYSCLKOUT/4 after reset, divider set by XCLKOUTDIV). |+| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19 (group 2, 8 mA), also external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive, or ECAP1 I/O, and may glitch at power-up when the internal VREG is used. |+| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 (group 2, 8 mA), also SPI-A slave output / master input or trip-zone input 3. |+| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 (group 2, 8 mA), also SPI-A slave input / master output or trip-zone input 2. |+| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 with alternate ePWM1 output B or direct output of comparator 1. |+| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with alternate ePWM1 output A (also HRPWM channel); PWM pins do not have pullups enabled at reset. |+| 30 | TEST | unconnected | TI-reserved test pin that must be left unconnected. |+| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 with alternate open-drain I2C-A data, ePWM external sync input, or ADC start-of-conversion A output. |+| 32 | VDD | power_in | CPU and logic digital supply; with the internal VREG enabled it is generated on-chip and needs at least 1.2 µF to ground at each VDD pin, or 1.71 V to 1.995 V when supplied externally with VREG disabled. |+| 33 | VSS | power_in | Digital ground. |+| 34 | VREGENZ | input | Internal regulator enable with internal pulldown: tie low to VSS to enable the internal 1.8 V VREG, or tie high to VDDIO to disable it and use an external 1.8 V supply. |+| 35 | VDDIO | power_in | Digital I/O and Flash supply, 2.97 V to 3.63 V (3.3 V nominal), requiring a decoupling capacitor sized by the system regulator. |+| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 with alternate open-drain I2C-A clock, ePWM external sync output, or ADC start-of-conversion B output. |+| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with alternate ePWM2 output A (also HRPWM channel). |+| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3 with alternate ePWM2 output B or direct output of comparator 2 (48-pin package only). |+| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with alternate ePWM3 output A (also HRPWM channel). |+| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5 with alternate ePWM3 output B or enhanced capture I/O 1. |+| 41 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 with alternate ePWM4 output A (also HRPWM channel), ePWM external sync input, or ePWM external sync output. |+| 42 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7 with alternate ePWM4 output B or SCI-A receive data. |+| 43 | VDD | power_in | CPU and logic digital supply; with the internal VREG enabled it is generated on-chip and needs at least 1.2 µF to ground at each VDD pin, or 1.71 V to 1.995 V when supplied externally with VREG disabled. |+| 44 | VSS | power_in | Digital ground. |+| 45 | X1 | input | 1.8 V on-chip crystal oscillator input that must never receive 3.3 V signals; connect to GND if unused, and use with X2 and a crystal or resonator when the oscillator is used. |+| 46 | X2 | output | On-chip crystal oscillator output, which must be connected across X1 to a crystal or ceramic resonator and left unconnected if unused. |+| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12 with alternate trip-zone input 1 or SCI-A transmit data. |+| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 (group 2, 8 mA) with alternate SCI receive data, open-drain I2C-A data, or trip-zone input 2. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-48(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `TMS320F28022PTT`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `tms320f28022ptt-etched.step` / `tms320f28022ptt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28022ptt.step` / `tms320f28022ptt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28020) (147 pp, sha256 `b90c388f4142c4b5`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320f28022ptt-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320f28022ptt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320f28022ptt.kicad_sym",+ "tms320f28022ptt.kicad_mod",+ "tms320f28022ptt.glb",+ "tms320f28022ptt.step",+ "tms320f28022ptt.lbr",+ "docs/hero.png",+ "docs/tms320f28022ptt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tms320f28022ptt-hero.glb",+ "tms320f28022ptt-hero.overlay.json"+ ],+ "component": {+ "mpn": "TMS320F28022PTT",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f28020",+ "parts": {+ "symbol": "tms320f28022ptt.kicad_sym",+ "footprint": "tms320f28022ptt.kicad_mod",+ "model_3d": "tms320f28022ptt-hero.glb",+ "model_3d_plain": "tms320f28022ptt.glb",+ "model_3d_step": "tms320f28022ptt-etched.step",+ "model_3d_step_plain": "tms320f28022ptt.step",+ "lbr": "tms320f28022ptt.lbr"+ },+ "distributor_links": {+ "lcsc": "C2860066",+ "digikey": "296-27541-ND",+ "mouser": "595-TMS320F28022PTT"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T01:40:55Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-27541-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TMS320F28022PTT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO29/SCITXDA/SCLA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 29 (group 2, 8 mA) with alternate SCI-A transmit, open-drain I2C-A clock, or trip-zone input 3."+ },+ {+ "number": "2",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset with internal pulldown; it must be held low during normal operation, and an external pullup (about 2.2 kΩ typical) is required so the device runs in functional mode."+ },+ {+ "number": "3",+ "name": "XRS",+ "type": "bidirectional",+ "description": "Open-drain device reset input and watchdog reset output with internal pullup, driven low on power-up, brown-out and watchdog reset; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required and any noise capacitor to VSS must be 100 nF or less."+ },+ {+ "number": "4",+ "name": "ADCINA6/AIO6",+ "type": "bidirectional",+ "description": "ADC group A channel 6 analog input, also selectable as digital AIO6 (AIO pins have no internal pullup)."+ },+ {+ "number": "5",+ "name": "ADCINA4/COMP2A/AIO4",+ "type": "bidirectional",+ "description": "ADC group A channel 4 input, also comparator 2A input (48-pin package only) and digital AIO4."+ },+ {+ "number": "6",+ "name": "ADCINA7",+ "type": "input",+ "description": "ADC group A channel 7 analog input."+ },+ {+ "number": "7",+ "name": "ADCINA3",+ "type": "input",+ "description": "ADC group A channel 3 analog input."+ },+ {+ "number": "8",+ "name": "ADCINA1",+ "type": "input",+ "description": "ADC group A channel 1 analog input."+ },+ {+ "number": "9",+ "name": "ADCINA2/COMP1A/AIO2",+ "type": "bidirectional",+ "description": "ADC group A channel 2 input, also comparator 1A input and digital AIO2."+ },+ {+ "number": "10",+ "name": "ADCINA0/VREFHI",+ "type": "input",+ "description": "ADC group A channel 0 analog input, which doubles as external ADC reference high (VREFHI) in external-reference mode and must not exceed VDDA."+ },+ {+ "number": "11",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog supply, 2.97 V to 3.63 V (3.3 V nominal), with about 2.2 µF typical capacitor placed near this pin."+ },+ {+ "number": "12",+ "name": "VSSA/VREFLO",+ "type": "power_in",+ "description": "Analog ground, also the ADC external reference low (VREFLO), which is always tied to ground."+ },+ {+ "number": "13",+ "name": "ADCINB1",+ "type": "input",+ "description": "ADC group B channel 1 analog input."+ },+ {+ "number": "14",+ "name": "ADCINB2/COMP1B/AIO10",+ "type": "bidirectional",+ "description": "ADC group B channel 2 input, also comparator 1B input and digital AIO10."+ },+ {+ "number": "15",+ "name": "ADCINB3",+ "type": "input",+ "description": "ADC group B channel 3 analog input."+ },+ {+ "number": "16",+ "name": "ADCINB4/COMP2B/AIO12",+ "type": "bidirectional",+ "description": "ADC group B channel 4 input, also comparator 2B input (48-pin package only) and digital AIO12."+ },+ {+ "number": "17",+ "name": "ADCINB6/AIO14",+ "type": "bidirectional",+ "description": "ADC group B channel 6 analog input, also digital AIO14."+ },+ {+ "number": "18",+ "name": "ADCINB7",+ "type": "input",+ "description": "ADC group B channel 7 analog input."+ },+ {+ "number": "19",+ "name": "GPIO34/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 34, also direct output of comparator 2 (48-pin only), and a boot-mode select pin sampled at reset."+ },+ {+ "number": "20",+ "name": "GPIO35/TDI",+ "type": "bidirectional",+ "description": "General-purpose I/O 35, also JTAG test data input with internal pullup, sampled on the rising edge of TCK; may glitch at power-up when the internal VREG is used."+ },+ {+ "number": "21",+ "name": "GPIO36/TMS",+ "type": "bidirectional",+ "description": "General-purpose I/O 36 (group 2, 8 mA), also JTAG test mode select input with internal pullup, sampled on the rising edge of TCK."+ },+ {+ "number": "22",+ "name": "GPIO37/TDO",+ "type": "bidirectional",+ "description": "General-purpose I/O 37 (group 2, 8 mA), also JTAG test data output shifted out on the falling edge of TCK and a boot-mode select pin sampled at reset."+ },+ {+ "number": "23",+ "name": "GPIO38/TCK/XCLKIN",+ "type": "bidirectional",+ "description": "General-purpose I/O 38, also JTAG test clock input with internal pullup and the default source for the external XCLKIN oscillator input (XCLKINSEL in XCLK register)."+ },+ {+ "number": "24",+ "name": "GPIO18/SPICLKA/SCITXDA/XCLKOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 18 (group 2, 8 mA), also SPI-A clock, SCI-A transmit, or XCLKOUT (SYSCLKOUT/4 after reset, divider set by XCLKOUTDIV)."+ },+ {+ "number": "25",+ "name": "GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 19 (group 2, 8 mA), also external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive, or ECAP1 I/O, and may glitch at power-up when the internal VREG is used."+ },+ {+ "number": "26",+ "name": "GPIO17/SPISOMIA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 17 (group 2, 8 mA), also SPI-A slave output / master input or trip-zone input 3."+ },+ {+ "number": "27",+ "name": "GPIO16/SPISIMOA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 16 (group 2, 8 mA), also SPI-A slave input / master output or trip-zone input 2."+ },+ {+ "number": "28",+ "name": "GPIO1/EPWM1B/COMP1OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 1 with alternate ePWM1 output B or direct output of comparator 1."+ },+ {+ "number": "29",+ "name": "GPIO0/EPWM1A",+ "type": "bidirectional",+ "description": "General-purpose I/O 0 with alternate ePWM1 output A (also HRPWM channel); PWM pins do not have pullups enabled at reset."+ },+ {+ "number": "30",+ "name": "TEST",+ "type": "unconnected",+ "description": "TI-reserved test pin that must be left unconnected."+ },+ {+ "number": "31",+ "name": "GPIO32/SDAA/EPWMSYNCI/ADCSOCAO",+ "type": "bidirectional",+ "description": "General-purpose I/O 32 with alternate open-drain I2C-A data, ePWM external sync input, or ADC start-of-conversion A output."+ },+ {+ "number": "32",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital supply; with the internal VREG enabled it is generated on-chip and needs at least 1.2 µF to ground at each VDD pin, or 1.71 V to 1.995 V when supplied externally with VREG disabled."+ },+ {+ "number": "33",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "34",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal regulator enable with internal pulldown: tie low to VSS to enable the internal 1.8 V VREG, or tie high to VDDIO to disable it and use an external 1.8 V supply."+ },+ {+ "number": "35",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O and Flash supply, 2.97 V to 3.63 V (3.3 V nominal), requiring a decoupling capacitor sized by the system regulator."+ },+ {+ "number": "36",+ "name": "GPIO33/SCLA/EPWMSYNCO/ADCSOCBO",+ "type": "bidirectional",+ "description": "General-purpose I/O 33 with alternate open-drain I2C-A clock, ePWM external sync output, or ADC start-of-conversion B output."+ },+ {+ "number": "37",+ "name": "GPIO2/EPWM2A",+ "type": "bidirectional",+ "description": "General-purpose I/O 2 with alternate ePWM2 output A (also HRPWM channel)."+ },+ {+ "number": "38",+ "name": "GPIO3/EPWM2B/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 3 with alternate ePWM2 output B or direct output of comparator 2 (48-pin package only)."+ },+ {+ "number": "39",+ "name": "GPIO4/EPWM3A",+ "type": "bidirectional",+ "description": "General-purpose I/O 4 with alternate ePWM3 output A (also HRPWM channel)."+ },+ {+ "number": "40",+ "name": "GPIO5/EPWM3B/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 5 with alternate ePWM3 output B or enhanced capture I/O 1."+ },+ {+ "number": "41",+ "name": "GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO",+ "type": "bidirectional",+ "description": "General-purpose I/O 6 with alternate ePWM4 output A (also HRPWM channel), ePWM external sync input, or ePWM external sync output."+ },+ {+ "number": "42",+ "name": "GPIO7/EPWM4B/SCIRXDA",+ "type": "bidirectional",+ "description": "General-purpose I/O 7 with alternate ePWM4 output B or SCI-A receive data."+ },+ {+ "number": "43",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital supply; with the internal VREG enabled it is generated on-chip and needs at least 1.2 µF to ground at each VDD pin, or 1.71 V to 1.995 V when supplied externally with VREG disabled."+ },+ {+ "number": "44",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "45",+ "name": "X1",+ "type": "input",+ "description": "1.8 V on-chip crystal oscillator input that must never receive 3.3 V signals; connect to GND if unused, and use with X2 and a crystal or resonator when the oscillator is used."+ },+ {+ "number": "46",+ "name": "X2",+ "type": "output",+ "description": "On-chip crystal oscillator output, which must be connected across X1 to a crystal or ceramic resonator and left unconnected if unused."+ },+ {+ "number": "47",+ "name": "GPIO12/TZ1/SCITXDA",+ "type": "bidirectional",+ "description": "General-purpose I/O 12 with alternate trip-zone input 1 or SCI-A transmit data."+ },+ {+ "number": "48",+ "name": "GPIO28/SCIRXDA/SDAA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 28 (group 2, 8 mA) with alternate SCI receive data, open-drain I2C-A data, or trip-zone input 2."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The text extraction of Figure 7-1 (48-pin LQFP) puts the labels in an order that conflicts with the ; TRST and XRS pin numbers are taken from table 7.2.1 (TRST=2, XRS=3); the figure text extraction for ; The datasheet lists TEST as I/O but states it is reserved and must remain unconnected; it is typed a"+ ],+ "pages_sent": 85,+ "cost_usd": 0.6253,+ "at": "2026-10-08T01:40:32"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f28020",+ "pages": 147,+ "sha256": "b90c388f4142c4b5",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tms320f28022ptt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tms320f28022ptt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b4830171f26b3f161c80770cd58f349de122b16a9df991bbfa230e6adba71ccb",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}